Full PDF Text Transcription for 80L186EC (Reference)
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80L186EC. For precise diagrams, and layout, please refer to the original PDF.
80C186EC 80C188EC AND 80L186EC 80L188EC 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS X Fully Static Operation X True CMOS Inputs and Outputs Y Integrated Feature Set Low-P...
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peration X True CMOS Inputs and Outputs Y Integrated Feature Set Low-Power Static Enhanced 8086 CPU Core Two Independent DMA Supported UARTs each with an Integral Baud Rate Generator Four Independent DMA Channels 22 Multiplexed I O Port Pins Two 8259A Compatible Programmable Interrupt Controllers Three Programmable 16-Bit Timer Counters 32-Bit Watchdog Timer Ten Programmable Chip Selects with Integral Wait-State Generator Memory Refresh Control Unit Power Management Unit On-Chip Oscillator System Level Testing Support (ONCE Mode) Y Direct Addressing Capability to 1 Mbyte Memory and 64 Kbyte I O Y Low-Power Operating Modes
80L186EC Datasheet
