80960HD Datasheet | Intel Corporation

80960HA/HD/HT 32-Bit High-Performance Superscalar Processor Data Sheet Advance Information Product Features s s s s s 32-Bit Parallel Architecture - Load/Store Architecture - Sixteen 32-Bit Global Registers - Sixteen 32-Bit Local Registers - 1.28 Gbyte Internal Bandwidth (80 MHz) - On-Chip Register Cache Processor Core Clock - 80960HA is 1x Bus Clock - 80960HD is 2x Bus Clock - 80960HT is 3x Bus Clock Binary patible with Other 80960 Processors Issue Up To 150 Million Instructions per Second High-Performance On-Chip Storage - 16 Kbyte Four-Way Set-Associative Instruction Cache - 8 Kbyte Four-Way Set-Associative Data Cache - 2 Kbyte General Purpose RAM - Separate 128-Bit Internal Paths For Instructions/Data s s s s s 3.3 V Supply Voltage - 5 V Tolerant Inputs - TTL patible Outputs Guarded Memory Unit - Provides Memory Protection - User/Supervisor Read/Write/Execute 32-Bit Demultiplexed Burst Bus - Per-Byte Parity Generation/Checking - Address Pipelining Option - Fully Programmable Wait State Generator - Supports 8-, 16- or 32-Bit Bus Widths - 160 Mbyte/s External Bandwidth (40 MHz) High-Speed Interrupt Controller - Up to 240 External Interrupts - 31 Fully Programmable Priorities - Separate, Non-maskable Interrupt Pin Dual On-Chip 32-Bit Timers...