Datasheet4U Logo Datasheet4U.com

82541ER - Gigabit Ethernet Controller

Description

Updated signal names to match design guide and reference schematics.

Added lead free information.

Added information about migrating from a 2-layer 0.36 mm wide-trace substrate to a 2-layer 0.32 mm wide-trace substrate.

Refer to the section on Package and Pinout Information.

Features

  • PCI Bus.
  • PCI revision 2.3, 32-bit, 33/66 MHz.
  • Algorithms that optimally use advanced PCI, MWI, MRM, and MRL commands.
  • 3.3 V (5 V tolerant PCI signaling) MAC Specific.
  • Low-latency transmit and receive queues.
  • IEEE 802.3x-compliant flow-control support with software-controllable thresholds.
  • Caches up to 64 packet descriptors in a single burst.
  • Programmable host memory receive buffers (256 B to 16 KB) and cache line.

📥 Download Datasheet

Datasheet Details

Part number 82541ER
Manufacturer Intel Corporation
File Size 348.63 KB
Description Gigabit Ethernet Controller
Datasheet download datasheet 82541ER Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
82541PI Gigabit Ethernet Controller Intel
8254 Tube AMPEREX
82540EM Gigabit Ethernet Controller Intel
825433 amp connector Framatome
82545EM Gigabit Ethernet Controller Intel

Other Datasheets by Intel Corporation

Part Number Description
8254 PROGRAMMABLE INTERVAL TIMER
82503 DUAL SERIAL TRANSCEIVER (DST)
8251A PROGRAMMABLE COMMUNICATION INTERFACE
82527 SERIAL COMMUNICATIONS CONTROLLER CONTROLLER AREA NETWORK PROTOCOL
8253 PROGRAMMABLE INTERVAL TIMER

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
www.DataSheet4U.com 82541ER Gigabit Ethernet Controller Networking Silicon Datasheet Product Features ■ ■ ■ PCI Bus — PCI revision 2.3, 32-bit, 33/66 MHz — Algorithms that optimally use advanced PCI, MWI, MRM, and MRL commands — 3.3 V (5 V tolerant PCI signaling) MAC Specific — Low-latency transmit and receive queues — IEEE 802.3x-compliant flow-control support with software-controllable thresholds — Caches up to 64 packet descriptors in a single burst — Programmable host memory receive buffers (256 B to 16 KB) and cache line size (16 B to 256 B) — Wide, optimized internal data path architecture — 64 KB configurable Transmit and Receive FIFO buffers PHY Specific — Integrated for 10/100/1000 Mb/s operation — IEEE 802.3ab Auto-Negotiation support — IEEE 802.
Published: |