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Intel Corporation

N82C55A Datasheet Preview

N82C55A Datasheet

CHMOS PROGRAMMABLE PERIPHERAL INTERFACE

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82C55A
CHMOS PROGRAMMABLE PERIPHERAL INTERFACE
Y Compatible with all Intel and Most
Other Microprocessors
Y High Speed ‘‘Zero Wait State’’
Operation with 8 MHz 8086 88 and
80186 188
Y 24 Programmable I O Pins
Y Low Power CHMOS
Y Completely TTL Compatible
Y Control Word Read-Back Capability
Y Direct Bit Set Reset Capability
Y 2 5 mA DC Drive Capability on all I O
Port Outputs
Y Available in 40-Pin DIP and 44-Pin PLCC
Y Available in EXPRESS
Standard Temperature Range
Extended Temperature Range
The Intel 82C55A is a high-performance CHMOS version of the industry standard 8255A general purpose
programmable I O device which is designed for use with all Intel and most other microprocessors It provides
24 I O pins which may be individually programmed in 2 groups of 12 and used in 3 major modes of operation
The 82C55A is pin compatible with the NMOS 8255A and 8255A-5
In MODE 0 each group of 12 I O pins may be programmed in sets of 4 and 8 to be inputs or outputs In
www.DataSheMfoeOrt4hDUaE.ncd1osmheaakcihnggraonudp
may be programmed to have 8 lines
interrupt control signals MODE 2 is
of
a
input or
strobed
output 3 of the remaining 4 pins
bi-directional bus configuration
are
used
The 82C55A is fabricated on Intel’s advanced CHMOS III technology which provides low power consumption
with performance equal to or greater than the equivalent NMOS product The 82C55A is available in 40-pin
DIP and 44-pin plastic leaded chip carrier (PLCC) packages
231256 – 31
Figure 1 82C55A Block Diagram
231256 – 1
231256 – 2
Figure 2 82C55A Pinout
Diagrams are for pin reference only Package
sizes are not to scale
October 1995
Order Number 231256-004




Intel Corporation

N82C55A Datasheet Preview

N82C55A Datasheet

CHMOS PROGRAMMABLE PERIPHERAL INTERFACE

No Preview Available !

82C55A
Symbol
PA3 – 0
RD
CS
GND
A1 – 0
www.DataSheet4U.com
PC7 – 4
PC0 – 3
PB0-7
VCC
D7 – 0
RESET
WR
PA7 – 4
NC
Pin Number
Dip PLCC
1–4 2–5
56
67
78
8– 9 9–10
10– 13 11 13–15
14– 17
18– 25
26
27– 34
35
16 – 19
20 – 22
24 – 28
29
30 – 33
35 – 38
39
36 40
37– 40 41–44
1 12
23 34
Table 1 Pin Description
Type
Name and Function
I O PORT A PINS 0 – 3 Lower nibble of an 8-bit data output latch
buffer and an 8-bit data input latch
I READ CONTROL This input is low during CPU read operations
I CHIP SELECT A low on this input enables the 82C55A to
respond to RD and WR signals RD and WR are ignored
otherwise
System Ground
I ADDRESS These input signals in conjunction RD and WR
control the selection of one of the three ports or the control
word registers
A1 A0 RD WR CS Input Operation (Read)
00010
Port A - Data Bus
01010
Port B - Data Bus
10010
Port C - Data Bus
1 1 0 1 0 Control Word - Data Bus
Output Operation (Write)
00100
Data Bus - Port A
01100
Data Bus - Port B
10100
Data Bus - Port C
11100
Data Bus - Control
Disable Function
XXXX1
Data Bus - 3 - State
XX1 1 0
Data Bus - 3 - State
I O PORT C PINS 4 – 7 Upper nibble of an 8-bit data output latch
buffer and an 8-bit data input buffer (no latch for input) This port
can be divided into two 4-bit ports under the mode control Each
4-bit port contains a 4-bit latch and it can be used for the control
signal outputs and status signal inputs in conjunction with ports
A and B
I O PORT C PINS 0 – 3 Lower nibble of Port C
I O PORT B PINS 0 – 7 An 8-bit data output latch buffer and an 8-
bit data input buffer
SYSTEM POWER a 5V Power Supply
I O DATA BUS Bi-directional tri-state data bus lines connected to
system data bus
I RESET A high on this input clears the control register and all
ports are set to the input mode
I WRITE CONTROL This input is low during CPU write
operations
I O PORT A PINS 4 – 7 Upper nibble of an 8-bit data output latch
buffer and an 8-bit data input latch
No Connect
2


Part Number N82C55A
Description CHMOS PROGRAMMABLE PERIPHERAL INTERFACE
Maker Intel Corporation
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