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N82C55A Datasheet CHMOS PROGRAMMABLE PERIPHERAL INTERFACE

Manufacturer: Intel Corporation

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Datasheet Details

Part number N82C55A
Manufacturer Intel Corporation
File Size 357.56 KB
Description CHMOS PROGRAMMABLE PERIPHERAL INTERFACE
Datasheet download datasheet N82C55A Datasheet

General Description

Symbol PA3–0 RD CS Pin Number Dip PLCC 1– 4 5 6 2–5 6 7 Type I O I I Name and Function PORT A PINS 0 – 3 Lower nibble of an 8-bit data output latch buffer and an 8-bit data input latch READ CONTROL This input is low during CPU read operations CHIP SELECT A low on this input enables the 82C55A to resp

Overview

82C55A CHMOS PROGRAMMABLE PERIPHERAL INTERFACE Y Compatible with all Intel and Most Other Microprocessors High Speed ‘‘Zero Wait State’’ Operation with 8 MHz 8086 88 and 80186 188 24 Programmable I O Pins Low Power CHMOS Completely TTL Compatible Y Y Y Control Word Read-Back Capability Direct Bit Set Reset Capability 2 5 mA DC Drive Capability on all I O Port Outputs Available in 40-Pin DIP and 44-Pin PLCC Available in EXPRESS Standard Temperature Range Extended Temperature Range Y Y Y Y Y Y The Intel 82C55A is a high-performance CHMOS version of the industry standard 8255A general purpose programmable I O device which is designed for use with all Intel and most other microprocessors It provides 24 I O pins which may be individually programmed in 2 groups of 12 and used in 3 major modes of operation The 82C55A is pin compatible with the NMOS 8255A and 8255A-5 In MODE 0 each group of 12 I O pins may be programmed in sets of 4 and 8 to be inputs or outputs In MODE 1 each group may be programmed to have 8 lines of input or output 3 of the remaining 4 pins are used www.DataSheet4U.

Key Features

  • or ‘‘personality’’ to further enhance the power and flexibility of the 82C55A Port A One 8-bit data output latch buffer and one 8-bit input latch buffer Both ‘‘pull-up’’ and ‘‘pulldown’’ bus hold devices are present on Port A Port B One 8-bit data input output latch buffer Only ‘‘pull-up’’ bus hold devices are present on Port B Port C One 8-bit data output latch buffer and one 8-bit data input buffer (no latch for input) This port can be divided into two 4-bit ports under the mode control Each 4.

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