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TE28F128J3A - Intel StrataFlash Memory (J3)

Download the TE28F128J3A datasheet PDF. This datasheet also covers the TE28F128J3C variant, as both devices belong to the same intel strataflash memory (j3) family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • Datasheet.
  • Performance.
  • Architecture.
  • 110/115/120/150 ns Initial Access Speed.
  • Multi-Level Cell Technology: High.
  • 125 ns Initial Access Speed (256 Mbit density only).
  • 25 ns Asynchronous Page mode Reads.
  • 30 ns Asynchronous Page mode Reads (256Mbit density only).
  • 32-Byte Write Buffer.
  • 6.8 µs per byte effective programming time.
  • Software Density at Low Cost.
  • High-Density Symmetrical 128-Kbyte Blocks.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (TE28F128J3C_Intel.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number TE28F128J3A
Manufacturer Intel Corporation
File Size 511.73 KB
Description Intel StrataFlash Memory (J3)
Datasheet download datasheet TE28F128J3A Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
TE28F128J3C Strata Flash Memory Intel
TE28F128J3D Embedded Flash Memory Intel
TE28F160S3 3 Volt and 5 Volt FlashFile Memory Intel
TE28F160S5 3 Volt and 5 Volt FlashFile Memory Intel
TE28F001BX 1-MBIT (128K x 8) BOOT BLOCK FLASH MEMORY Intel

Other Datasheets by Intel Corporation

Part Number Description
TE28F128P30 (TE28FxxxP30) Strata Flash Embedded Memory
TE28F160B3 (TE28Fxxx) 3 Volt Advanced Boot Block Flash Memory
TE28F160C3 (TE28Fxxx) 3 Volt Advanced Boot Block Flash Memory
TE28F256J3C Strata Flash Memory
TE28F256P30 (TE28FxxxP30) Strata Flash Embedded Memory

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
Intel StrataFlash® Memory (J3) 256-Mbit (x8/x16) Product Features Datasheet ■ Performance ■ Architecture — 110/115/120/150 ns Initial Access Speed — Multi-Level Cell Technology: High — 125 ns Initial Access Speed (256 Mbit density only) — 25 ns Asynchronous Page mode Reads — 30 ns Asynchronous Page mode Reads (256Mbit density only) — 32-Byte Write Buffer —6.8 µs per byte effective programming time ■ Software Density at Low Cost — High-Density Symmetrical 128-Kbyte Blocks —256 Mbit (256 Blocks) (0.