Full PDF Text Transcription for IRS2453D (Reference)
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IRS2453D. For precise diagrams, and layout, please refer to the original PDF.
IRS2453(1)D(S) Product Summary Topology VOFFSET Io+ & I o- (typical) Deadtime (typical) Full-bridge 600 V 180 mA & 260 mA 1.0 μs (IRS2453D) 0.5 μs (IRS24531D) Features ...
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600 V 180 mA & 260 mA 1.0 μs (IRS2453D) 0.5 μs (IRS24531D) Features Integrated 600 V full-bridge gate driver CT, RT programmable oscillator 15.6 V Zener clamp on VCC Micropower startup Logic level latched shutdown pin Non-latched shutdown on CT pin (1/6th VCC) Internal bootstrap FETs Excellent latch immunity on all inputs & outputs ESD protection on all pins 14-lead SOIC or PDIP package 0.5 or 1.0μs (typ.
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