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Intersil Electronic Components Datasheet

BBT3420 Datasheet

Quad 2.488-3.1875Gbps/Channel Transceiver

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®
Data Sheet
September 14, 2005
BBT3420
FN7481.1
Quad 2.488-3.1875Gbps/Channel Transceiver
1 Features
• Four channels of transmitter and receiver with serial data
transfer rates of 2.488-3.1875Gbps/channel with full rate
and half-rate operations
• Up to 12.75Gbps data rate at full duplex
• User-controlled dual-speed operation (per channel) 2.488-
3.1875Gbps or 1.244-1.59Gbps
• IEEE 802.3ae-2002 10 GE and 10 GFC compliant
- XAUI, XGMII, and MDC/MDIO interfaces
• XGMII format 10-bit parallel input/output data
- Supports HSTL 1.8V and 2.5V SSTL_2
• Extensive configuration via 802.3-compliant MDC/MDIO
serial interface
• 8bit/10bit Encoding/Decoding per channel with selectable
parallel input/output data sizes
- Support optional 8b/10b encoder/decoder bypass
operation
• Integrated Equalization and Pre-emphasis
• De-skewing and channel-to-channel alignment options
• Low power, 250mW per channel typical
• Meets jitter requirements with significant margin
• Comma detection and synchronization, byte alignment
• Tx/Rx rate matching via IDLE insertion/deletion
• Receive signal detect and 16 levels of transmission
medium equalization
• CML transmit outputs with four levels of pre-emphasis
• Loopback
- Per-channel serial Tx-to-Rx and Rx-to-Tx parallel
internal loopback modes
• Single-ended/differential input Reference clock
• Double Data-Rate (DDR) mode, also optional SDR (Single
Data Rate) on transmitter
• Support both source-centered and source-simultaneous
clocking
• Long Run Length (512 bit) frequency lock ideal for
proprietary encoding schemes Transmit byte clock
schemes
- One Transmit Byte Clock (TBC) for each channel, or
one TBC for all four channels
• Received clock schemes
- Receive data aligned to local reference clock, to
recovered clock for each channel, or to recovered clock
for Channel A only
• Supports Built-In Self Test (BIST) and IEEE 1149.1 JTAG
• On-chip 25series output terminations (XGMII side)
• Standard 0.18µm 1.8V CMOS technology
• 3.3V tolerant I/O
Switch Card
nPower BBT 3420
Transceiver
XAUI
Up to 40"
nPower BBT 3420
Transceiver
XGMII
Serial 10 Gigabit
10GBASE-R
Custom ASIC
&
MAC Functions
XGMII
nPower BBT 3420
Transceiver
XXAAUUII
Optical
Transponder
Switch
Fabric
nPower BBT 3420
Transceiver
XAUI
Up to 40"
nPower BBT 3420
Transceiver
XGMII
WDM 10 Gigabit
10GBASE-LX4
Custom ASIC
&
MAC Functions
XGMII
nPower BBT 3420
Transceiver
XXAAUUII
WDM
Optical
Transponder
FIGURE 1-1. EXAMPLE BACKPLANE AND LINE CARD APPLICATIONS
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2004, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.


Intersil Electronic Components Datasheet

BBT3420 Datasheet

Quad 2.488-3.1875Gbps/Channel Transceiver

No Preview Available !

BBT3420
RFCP
RFCN
TXAP
TXAN
RXAP
RXAN
TXBP
TXBN
RXBP
RXBN
TXCP
TXCN
RXCP
RXCN
TXDP
TXDN
RXDP
RXDN
SIG_DET
JTAG
TAP
MDIO Register File & Common Logic
20X or 10X
Transmit Clock
Generator
HS_TX_CLK
REF_CLK
TX+
TX-
RX+
RX-
RFCN
SIGDET
SSTL or HSTL
Input
Reference
Channel A
TD[9:0]
TBC
RD[9:0]
RBC
CODE
MDIO Protocol
Engine
Internal
Nodes
HS_TX_CLK
REF_CLK
TX+
TX-
RX+
RX-
RFCN
SIGDET
Channel B
TD[9:0]
TBC
RD[9:0]
RBC
CODE
HS_TX_CLK
REF_CLK
TX+
TX-
RX+
RX-
RFCN
SIGDET
Channel C
TD[9:0]
TBC
RD[9:0]
RBC
CODE
HS_TX_CLK
REF_CLK
TX+
TX-
RX+
RX-
RFCN
SIGDET
Channel D
SIGNAL
DETECT
LOGIC
TD[9:0]
TBC
RD[9:0]
RBC
CODE
FIGURE 1-2. BBT3420 BLOCK DIAGRAM
REFP(N.C.)
REFN(N.C.)
RREF(N.C.)
VREF
TDA[9:0]
TCA
RDA[9:0]
RCA
TDB[9:0]
TCB
RDB[9:0]
RCB
TDC[9:0]
TCC
RDC[9:0]
RCC
TDD[9:0]
TCD
RDD[9:0]
RCD
PSYNC
CODE
2


Part Number BBT3420
Description Quad 2.488-3.1875Gbps/Channel Transceiver
Maker Intersil
Total Page 30 Pages
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