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IH5043 Datasheet

Dual SPDT CMOS Analog Switch

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IH5043TM
Data SPOheSeStOIBBLSEOSLUEBHTSEI-T5PI0TR4UO3TDEUPCRTODUCMTarch 2000
File Number 3130.3
Dual SPDT CMOS Analog Switch
[ /Title
(IH504
3)
/Sub-
ject
(Dual
SPDT
CMOS
Ana-
log
Switch
)
/Autho
r ()
/Key-
words
(Inter-
sil
Corpo-
ration,
semi-
con-
ductor,
Dual
SPDT
CMOS
Ana-
log
Switch
)
/Cre-
ator ()
/DOCI
NFO
pdf-
mark
[
The IH5043 analog switch uses an improved, high voltage
CMOS monolithic technology. These devices provide ease
of use and performance advantages not previously
available from solid state switches.
Key performance advantage is TTL compatibility and ultra
low power operation. The quiescent current requirement is
less than 1mA. Also, the IH5043 guarantees Break-Before-
Make switching, accomplished by extending the tON time
(300ns Typ), so that it exceeds tOFF time (200ns Typ). This
insures that an ON channel will be turned OFF before an
OFF channel can turn ON. The need for external logic
required to avoid channel to channel shorting during
switching is eliminated.
Part Number Information
TEMP.
PART NUMBER RANGE (oC)
PACKAGE
IH5043CPE
IH5043CY
0 to 70
0 to 70
16 Ld PDIP
16 Ld SOIC
PKG.
NO.
E16.3
M16.15
Schematic Diagram
FUNCTIONAL DRIVER, TYPICAL DRIVER, GATE (1/2 AS SHOWN)
V+
Q3
5K
Q4
Q1
2K
Q9
S1 FLOATS D1
GND
IN
VL
Q2
Q10
Q11
10K
Q5
400
1K
S3 FLOATS D3
Q12
Q7
Q6 Q8
400
V-
Features
• See HI504X for Other Functions
• Dual SPDT
• Switches Greater than 20VP-P Signals with ±15V Supplies
• Quiescent Current Less than 1mA
• Break-Before-Make Switching tOFF 200ns, tON 300ns (Typ)
• TTL, DTL, CMOS, PMOS Compatible
Pinout
IH5043
(PDIP, SOIC)
TOP VIEW
D1 1
NC 2
D3 3
S3 4
S4 5
D4 6
NC 7
D2 8
16 S1
15 IN1
14 V-
13 GND
12 VL
11 V+
10 IN2
9 S2
Functional Diagram
S1 16
S3 4
VL
12
V+
11
1
D1
3 D3
IN1 15
IN2 10
S2 9
8 D2
S4 5
13
6
14
D4
GND
V-
SWITCH STATES SHOWN ARE FOR LOGIC “1” INPUT
LOGIC
0
1
TRUTH TABLE
SWITCH 1, 2
Off
On
SWITCH 3, 4
On
Off
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000


Intersil Electronic Components Datasheet

IH5043 Datasheet

Dual SPDT CMOS Analog Switch

No Preview Available !

IH5043
Absolute Maximum Ratings
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <36V
V+ to VD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <30V
VD to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <30V
VD to VS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .<±22V
VL to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <33V
VL to VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <30V
VL to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <20V
VIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <20V
Continuous Current (S-D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30mA
Peak Current S-D (Pulsed 1ms, 10% Duty Cycle Max) . . . . . . 70mA
Thermal Information
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
115
Maximum Junction Temperature (Plastic Packages) . . . . . . .150oC
Maximum Storage Temperature. . . . . . . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications V+ = +15V, V- = -15V, VL = +5V
PER CHANNEL PARAMETER
TEST CONDITIONS
DYNAMIC CHARACTERISTICS
Turn ON Time, tON
Turn OFF Time, tOFF
Charge Injection, Q
RL = 1k, VANALOG = -10V to +10V, See
Figure 6
See Figure 7
OFF Isolation, OIRR
Crosstalk, CCRR
f = 1MHz, RL = 100, CL 5pF, See Figure 4
One Channel Off; Any Other Channel
Switches as per Figure 3
DIGITAL INPUT CHARACTERISTICS
Input Logic Current, IIN(ON)
Input Logic Current, IIN(OFF)
ANALOG SWITCH CHARACTERISTICS
VIN = 2.4V
VIN = 0.8V
Drain-Source ON Resistance, rDS(ON)
IS = 10mA, VANALOG = -10V to +10V
Channel-to-Channel rDS(ON) Match, rDS(ON)
Minimum Analog Signal Handling Capability, VANALOG
Switch OFF Leakage Current, ID(OFF), IS(OFF)
VANALOG = -10V to +10V
Switch ON Leakage Current, ID(ON)+IS(ON)
VD = VS = -10V to +10V
POWER SUPPLY CHARACTERISTICS
+ Power Supply Quiescent Current, I+
- Power Supply Quiescent Current, I-
+5V Supply Quiescent Current, IL
Ground Quiescent Current, IGND
NOTES:
2. Typical values are for design aid only, not guaranteed and not subject to production testing.
3. Min or Max value unless otherwise specified.
(NOTES 2, 3)
0oC
25oC
70oC
- 1000 -
- 500 -
- 20 (Typ) -
- 50 (Typ) -
- -50 (Typ) -
±1 ±1 10
±1 ±1 10
80 80 130
- 30 (Typ) -
- ±10 (Typ) -
- ±5 100
- ±10 100
10 10 100
10 10 100
10 10 100
10 10 100
UNITS
ns
ns
mV
dB
dB
µA
µA
V
nA
nA
µA
µA
µA
µA
2


Part Number IH5043
Description Dual SPDT CMOS Analog Switch
Maker Intersil
Total Page 7 Pages
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