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Intersil Electronic Components Datasheet

68HC68W1 Datasheet

CMOS Serial Digital Pulse Width Modulator

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CDP68HC68W1
March 1998
CMOS Serial Digital Pulse Width Modulator
Features
Description
• Programmable Frequency and Duty Cycle Output
• Serial Bus Input; Compatible with Motorola/Intersil
SPI Bus, Simple Shift-Register Type Interface
• 8 Lead PDIP Package
• Schmitt Trigger Clock Input
• 4V to 6V Operation, -40oC to 85oC Temperature Range
• 8MHz Clock Input Frequency
Pinout
CDP68HC68W1
(PDIP)
TOP VIEW
CLK 1
CS 2
8 VDD
7 PWM
The CDP68HC68W1 modulates a clock input to supply a
variable frequency and duty-cycle output signal. Three 8-bit
registers (pulse width, frequency and control) are accessed
serially after power is applied to initialize device operation.
The value in the pulse width register selects the high
duration of the output period. The frequency register byte
divides the clock input frequency and determines the overall
output clock period. The input clock can be further divided by
two or a low power mode may be selected by the lower two
bits in the control register. A comparator circuit allows
threshold control by setting the output low if the input at the
VT pin rises above 0.75V. The CDP68HC68W1 is supplied in
an 8 lead PDIP package (E suffix).
Ordering Information
TEMP. RANGE
PART NUMBER
(oC)
PACKAGE
PKG.
NO.
VT 3
VSS 4
6 SCK
5 DATA
CDP68HC68W1E
-40 to 85
8 Ld PDIP
E8.3
Block Diagram
CLK
8 - STAGE RIPPLE
COUNTER
INPUT CLK
MODULATOR
LOGIC
PULSE - WIDTH
DATA REGISTER
RESET
LOAD
PWM
8 - STAGE RIPPLE
COUNTER
FREQUENCY
LOAD
DATA REGISTER
DATA
VT
8 - STAGE SHIFT
REGISTER
VT
COMPARATOR
SCK
8 - STAGE SHIFT
REGISTER
CONTROL REGISTER
2 - STAGE SHIFT
LOAD
8 16
5 - STAGE 24 - STATE
COMPARATOR
24
CS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
File Number 1919.3


Intersil Electronic Components Datasheet

68HC68W1 Datasheet

CMOS Serial Digital Pulse Width Modulator

No Preview Available !

CDP68HC68W1
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . . -0.5V to +7V
(Voltage Referenced to VSS Terminal)
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V
DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
99
Device Dissipation Per Output Transistor . . . . . . . . . . . . . . . 100mW
Maximum
Maximum
Storage Temperature Range (TSTG) .
Lead Temperature (During Soldering)
.
.
.
.
.-65oC
......
to
..
150oC
265oC
At Distance 1/16 ±1/32 in. (1.59 ± 0.79mm)
From Case for 10s Max
TA = Full Package Temperature Range (All Package Types)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
PARAMETER
SYMBOL
CDP68HC68W1, VDD = 5V ±10%, VSS = 0V, TA = -40oC to 85oC
DC Operating Voltage Range
-
MIN
4
TYP
-
MAX
UNITS
6V
Input Voltage Range (Except VT Pin)
VT Pin Output Voltage Threshold
Device Current in “Power Down” Mode, Clock Disabled
Low Level Output Voltage (IOL = 1.6mA)
High Level Output Voltage (IOH = -1.6mA)
Input Leakage Current
Operating Device Current (fCLK = 1MHz)
Clock Input Capacitance
(VIN = 0V, fCLK = 1MHz, TA = 25oC)
VIH 0.7•VDD
- VDD+0.3V V
VIL -0.3
- 0.3•VDD V
VIT 0.4
- 0.15•VDD V
IPD - - 1 µA
VOL -
- 0.4 V
VOH
VDD - 0.4V
-
-
V
IIN -
- ±1 µA
IOPER
-
-
1 mA
CIN -
- 10 pF
Control Timing
PARAMETER
CDP68HC68W1, VDD = 5V ±10%, VSS = 0V, TA = -40oC to 85oC
Clock Frequency
Cycle Time
Clock to PWM Out
Clock High Time
Clock Low Time
Rise Time (20% VDD to 70% VDD)
Fall Time (70% VDD to 20% VDD)
SYMBOL
MIN
FCLK
tCYC
tPWMO
tCLKH
tCLKL
tR
tF
DC
-
-
50
50
-
-
MAX
UNITS
8.0 MHz
- ns
125 ns
- ns
- ns
100 ns
100 ns
2


Part Number 68HC68W1
Description CMOS Serial Digital Pulse Width Modulator
Maker Intersil Corporation
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