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Intersil Electronic Components Datasheet

CD40194BMS Datasheet

CMOS 4-Bit Bidirectional Universal Shift Register

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December 1992
CD40104BMS,
CD40194BMS
CMOS 4-Bit Bidirectional
Universal Shift Register
Features
• High Voltage Type (20V Rating)
• Medium Speed fCL = 12MHz (typ.) at VDD = 10V
• Fully Static Operation
• Synchronous Parallel or Serial Operation
• Three State Outputs (CD40104BMS)
• Asynchronous Master Reset (CD40194BMS)
• 5V, 10V and 15V Parametric Ratings
• Standardized Symmetrical Output Characteristics
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Applications
• Arithmetic Unit Bus Registers
• Serial/Parallel Conversions
• General Purpose Register for Bus Organized Systems
• General Purpose Registers
Description
The CD40104BMS is a universal shift register featuring parallel
inputs, parallel outputs, SHIFT RIGHT and SHIFT LEFT serial
inputs, and a high impedance third output state allowing the device
to be used in bus organized systems.
In the parallel load mode (S0 and S1 are high), data is loaded into
the associated flip-flop and appears at the output after the positive
transition of the CLOCK input. During loading, serial data flow is
inhibited. Shift right and shift left are accomplished synchronously
on the positive clock edge with serial data entered at the SHIFT
RIGHT and SHIFT LEFT serial inputs, respectively. Clearing the
register is accomplished by setting both mode controls low and
clocking the register. When the output enable input is low, all outputs
assume the high impedance state.
The CD40194BMS is a universal shift register featuring parallel inputs,
parallel outputs SHIFT RIGHT and SHIFT LEFT serial inputs, and a
direct overriding clear input. In the parallel load mode (S0 and S1 are
high), data is loaded into the associated flip-flop and appears at the out-
put after the positive transition of the CLOCK input. During loading,
serial data flow is inhibited. Shift right and shift left are accomplished
synchronously on the positive clock edge with data entered at the
SHIFT RIGHT and SHIFT LEFT serial inputs, respectively. Clocking of
the register is inhibited when both mode control inputs are low. When
low, the RESET input resets all stages and forces all outputs low. The
CD40194BMS is similar to industry types 340194 and MC40194.
The CD40104BMS and CD40194BMS series types are supplied in
these 16 lead outline packages
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
* CD40104B Only
*HNX, †H4W
*H1L, †HIF
H6W
†CD40194B Only
Pinouts
CD40104BMS
TOP VIEW
OUTPUT ENABLE 1
SHIFT RIGHT IN 2
D0 3
D1 4
D2 5
D3 6
SHIFT LEVEL IN 7
VSS 8
16 VDD
15 Q0
14 Q1
13 Q2
12 Q3
11 CLOCK
10 SELECT 1
9 SELECT 0
CD40194BMS
TOP VIEW
RESET 1
SHIFT RIGHT IN 2
D0 3
D1 4
D2 5
D3 6
SHIFT LEVEL IN 7
VSS 8
16 VDD
15 Q0
14 Q1
13 Q2
12 Q3
11 CLOCK
10 SELECT 1
9 SELECT 0
Functional Diagrams
CD40104BMS
OUTPUT ENABLE
3
D0
4
D1
D2 5
D3 6
7
SHIFT LEFT IN
2
SHIFT RIGHT IN 9
S0
MODE SELECT S1 10
CLOCK
1
11
15
Q0
14
Q1
13 Q2
12 Q3
VDD = 16
VSS = 8
CD40194BMS
RESET
3
D0
4
D1
5
D2
D3 6
7
SHIFT LEFT IN 2
SHIFT RIGHT IN 9
S0
MODE SELECT
10
S1
CLOCK
1
11
15
Q0
14
Q1
13
Q2
12 Q3
VDD = 16
VSS = 8
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1307
File Number 3352


Intersil Electronic Components Datasheet

CD40194BMS Datasheet

CMOS 4-Bit Bidirectional Universal Shift Register

No Preview Available !

Specifications CD40104BMS, CD40194BMS
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
Reliability Information
Thermal Resistance . . . . . . . . . . . . . . . .
θja
Ceramic DIP and FRIT Package . . . . . 80oC/W
θjc
20oC/W
Flatpack Package . . . . . . . . . . . . . . . . 70oC/W
20oC/W
Maximum Package Power Dissipation (PD) at +125oC
For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW
For TA = +100oC to +125oC (Package Type D, F, K). . . . . . Derate
Linearity at 12mW/oC to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Supply Current
Input Leakage Current
SYMBOL
CONDITIONS (NOTE 1)
GROUP A
SUBGROUPS
IDD VDD = 20V, VIN = VDD or GND
1
2
VDD = 18V, VIN = VDD or GND
3
IIL VIN = VDD or GND VDD = 20V
1
2
TEMPERATURE
+25oC
+125oC
-55oC
+25oC
+125oC
LIMITS
MIN MAX UNITS
- 10 µA
- 1000 µA
- 10 µA
-100
-
nA
-1000 -
nA
Input Leakage Current
VDD = 18V
IIH VIN = VDD or GND VDD = 20V
Output Voltage
VDD = 18V
VOL15 VDD = 15V, No Load
3
1
2
3
1, 2, 3
-55oC
+25oC
+125oC
-55oC
+25oC, +125oC, -55oC
-100
-
-
-
-
-
100
1000
100
50
nA
nA
nA
nA
mV
Output Voltage
Output Current (Sink)
Output Current (Sink)
VOH15
IOL5
IOL10
VDD = 15V, No Load (Note 3)
VDD = 5V, VOUT = 0.4V
VDD = 10V, VOUT = 0.5V
1, 2, 3
1
1
+25oC, +125oC, -55oC
+25oC
+25oC
14.95
0.53
1.4
-
-
-
V
mA
mA
Output Current (Sink)
Output Current (Source)
Output Current (Source)
Output Current (Source)
Output Current (Source)
IOL15
IOH5A
IOH5B
IOH10
IOH15
VDD = 15V, VOUT = 1.5V
VDD = 5V, VOUT = 4.6V
VDD = 5V, VOUT = 2.5V
VDD = 10V, VOUT = 9.5V
VDD = 15V, VOUT = 13.5V
1
+25oC
3.5 - mA
1
+25oC
- -0.53 mA
1
+25oC
- -1.8 mA
1
+25oC
- -1.4 mA
1
+25oC
- -3.5 mA
N Threshold Voltage
P Threshold Voltage
Functional
Input Voltage Low
(Note 2)
Input Voltage High
(Note 2)
Input Voltage Low
(Note 2)
Input Voltage High
(Note 2)
Tri-State Output
Leakage
Tri-State Output
Leakage
VNTH
VPTH
F
VIL
VDD = 10V, ISS = -10µA
VSS = 0V, IDD = 10µA
VDD = 2.8V, VIN = VDD or GND
VDD = 20V, VIN = VDD or GND
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
VDD = 5V, VOH > 4.5V, VOL < 0.5V
VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V
VIL
VIH
IOZL
IOZH
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
VIN = VDD or GND VDD = 20V
VOUT = 0V
VIN = VDD or GND
VOUT = VDD
VDD = 18V
VDD = 20V
VDD = 18V
1
1
7
7
8A
8B
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1
2
3
1
2
3
+25oC
-2.8 -0.7
+25oC
0.7 2.8
+25oC
VOH > VOL <
+25oC
VDD/2 VDD/2
+125oC
-55oC
+25oC, +125oC, -55oC -
1.5
V
V
V
V
+25oC, +125oC, -55oC 3.5
-
V
+25oC, +125oC, -55oC -
4V
+25oC, +125oC, -55oC 11 - V
+25oC
+125oC
-55oC
+25oC
+125oC
-55oC
-0.4 - µA
-12 - µA
-0.4 - µA
- 0.4 µA
- 12 µA
- 0.4 µA
NOTES: 1. All voltages referenced to device GND, 100% testing being 3. For accuracy, voltage is measured differentially to VDD. Limit
implemented.
is 0.050V max.
2. Go/No Go test with limits applied to inputs.
7-1308


Part Number CD40194BMS
Description CMOS 4-Bit Bidirectional Universal Shift Register
Maker Intersil Corporation
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CD40194BMS Datasheet PDF






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