CD40208BMS Description
The CD40208BMS is a 4 x 4 multiport register containing four 4-bit registers, write address decoder, two separate read address decoders, and two 3-state output buses. When the ENABLE input is low, the corresponding output bus is switched, independently of the clock, to a high impedance state. The high impedance third state provides the outputs with the capability of being connected to the bus lines in a bus...
CD40208BMS Key Features
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V Meets All Requirements of JEDEC Tentative Standards No. 13B, “Standard Specifications for Description o