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Intersil Electronic Components Datasheet

CD4031BMS Datasheet

CMOS 64-Stage Static Shift Register

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CD4031BMS
December 1992
CMOS 64-Stage Static Shift Register
Features
Description
• High Voltage Type (20V Rating)
• Fully Static Operation: DC to 12MHz (typ.) at VDD -
VSS = 15V
• Standard TTL Drive Capability on Q Output
• Recirculation Capability
• Three Cascading Modes:
- Direct Clocking for High-Speed Operation
- Delayed Clocking for Reduced Clock Drive Require-
ments
- Additional 1/2 Stage for Slow Clocks
• 100% Tested For Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full
Package-Temperature Range;
- 100nA at 18V and +25oC
• Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Applications
• Serial Shift Registers
• Time Delay Circuits
The CD4031BMS is a static shift register that contains 64 D-
type, master-slave flip-flop stages and one stage which is a
D-type master flip-flop only (referred to as a 1/2 stage).
The logic level present at the DATA input is transferred into
the first stage and shifted one stage at each positive-going
clock transition. Maximum clock frequencies up to 12MHz
(typical) can be obtained. Because fully static operation is
allowed, information can be permanently stored with the
clock line in either the low or high state. The CD4031BMS
has a MODE CONTROL input that, when in the high state,
allows operation in the recirculating mode. The MODE CON-
TROL input can also be used to select between two sepa-
rate data sources. Register packages can be cascaded and
the clock lines driven directly for high-speed operation. Alter-
natively, a delayed clock output (CLD) is provided that
enables cascading register packages while allowing reduced
clock drive fan-out and transition-time requirements. A third
cascading option makes use of the Q’ output from the 1/2
stage, which is available on the next negative-going transi-
tion of the clock after the Q output occurs. This delayed out-
put, like the delayed clock CLD, is used with clocks having
slow rise and fall times.
The CD4031BMS is supplied in these 16 lead outline pack-
ages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4X
H1F
H6W
Pinout
CD4031BMS
TOP VIEW
RECIRCULATE
DATA IN 2 1
CLOCK INHIBIT 2
NC 3
NC 4
Q’ 5
Q6
Q7
VSS 8
16 VDD
15 DATA IN 1
14 NC
13 NC
12 NC
11 NC
10 MODE CONTROL
9 CLD
NC = NO CONNECTION
Functional Diagram
DATA 1 15
IN
MODE 10
CONT.
RECIRC 1
DATA 2
IN
CONTROL
LOGIC
CLOCK 2
IN
CLOCK
LOGIC
64
STAGES
DATA
OUT
6
DATA
OUT
CL 7
CL
9
DELAYED
VDD = 16
VSS = 8
CLOCK
OUT
NC = 3, 4, 11, 12, 13, 14
1/2
STAGE
Q’
5
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-816
File Number 3306


Intersil Electronic Components Datasheet

CD4031BMS Datasheet

CMOS 64-Stage Static Shift Register

No Preview Available !

Specifications CD4031BMS
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
Reliability Information
Thermal Resistance . . . . . . . . . . . . . . . .
θja
Ceramic DIP and FRIT Package . . . . . 80oC/W
θjc
20oC/W
Flatpack Package . . . . . . . . . . . . . . . . 70oC/W
20oC/W
Maximum Package Power Dissipation (PD) at +125oC
For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW
For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate
Linearity at 12mW/oC to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP A
LIMITS
PARAMETER
SYMBOL
CONDITIONS (NOTE 1)
SUBGROUPS TEMPERATURE MIN MAX UNITS
Supply Current
IDD VDD = 20V, VIN = VDD or GND
1
+25oC
- 10 µA
2
+125oC
- 1000 µA
VDD = 18V, VIN = VDD or GND
3
-55oC
- 10 µA
Input Leakage Current
IIL VIN = VDD or GND VDD = 20
1
+25oC
-100
-
nA
2
+125oC
-1000 -
nA
VDD = 18V
3
-55oC
-100
-
nA
Input Leakage Current
IIH VIN = VDD or GND VDD = 20
1
+25oC
- 100 nA
2
+125oC
- 1000 nA
VDD = 18V
3
-55oC
- 100 nA
Output Voltage
VOL15 VDD = 15V, No Load
1, 2, 3
+25oC, +125oC, -55oC -
50 mV
Output Voltage
VOH15 VDD = 15V, No Load (Note 3)
1, 2, 3
+25oC, +125oC, -55oC 14.95
-
V
Output Current
IOL5 VDD = 5V, VOUT = 0.4V
1
+25oC
0.51 - mA
Q, Q’, CLD
IOL10 VDD = 10V, VOUT = 0.5V
1
+25oC
1.3 - mA
IOL15 VDD = 15V, VOUT = 1.5V
1
+25oC
3.4 - mA
Output Current Q
IOL5 VDD = 5V, VOUT = 0.4V
1
+25oC
2.04 - mA
Output Current Q
IOL10 VDD = 10V, VOUT = 0.5V
1
+25oC
5.2 - mA
Output Current Q
IOL15 VDD = 15V, VOUT = 1.5V
1
+25oC
13.6 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V
1
+25oC
- -0.51 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V
1
+25oC
- -1.6 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V
1
+25oC
- -1.3 mA
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V
1
+25oC
- -3.4 mA
N Threshold Voltage
VNTH VDD = 10V, ISS = -10µA
1
+25oC
-2.8 -0.7 V
P Threshold Voltage
VPTH VSS = 0V, IDD = 10µA
1
+25oC
0.7 2.8
V
Functional
F VDD = 2.8V, VIN = VDD or GND
7
+25oC
VOH > VOL < V
VDD = 20V, VIN = VDD or GND
7
+25oC
VDD/2 VDD/2
VDD = 18V, VIN = VDD or GND
8A
+125oC
VDD = 3V, VIN = VDD or GND
8B
-55oC
Input Voltage Low
VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC -
1.5 V
(Note 2)
Input Voltage High
VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5
-
V
(Note 2)
Input Voltage Low
VIL VDD = 15V, VOH > 13.5V,
1, 2, 3
+25oC, +125oC, -55oC -
4V
(Note 2)
VOL < 1.5V
Input Voltage High
VIH VDD = 15V, VOH > 13.5V,
1, 2, 3
+25oC, +125oC, -55oC 11
-
V
(Note 2)
VOL < 1.5V
NOTES: 1. All voltages referenced to device GND, 100% testing being 3. For accuracy, voltage is measured differentially to VDD. Limit
implemented.
is 0.050V max.
2. Go/No Go test with limits applied to inputs.
7-817


Part Number CD4031BMS
Description CMOS 64-Stage Static Shift Register
Maker Intersil Corporation
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CD4031BMS Datasheet PDF






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