900,000+ datasheet pdf search and download

Datasheet4U offers most rated semiconductors data sheet pdf




Intersil Electronic Components Datasheet

CD4033BMS Datasheet

CMOS Decade Counter/Divider

No Preview Available !

CD4033BMS
December 1992
CMOS Decade Counter/Divider
Features
Description
• High Voltage Types (20V Rating)
• Decoded 7 Segment Display Outputs and Ripple
Blanking
• Counter and 7 Segment Decoding in One Package
• Easily Interfaced with 7 Segment Display Types
• Fully Static Counter Operation DC to 6MHz (typ.) at VDD =
10V
• Ideal for Low-Power Displays
• “Ripple Blanking” and Lamp Test
• 100% Tested for Quiescent Current at 20V
• Standardized Symmetrical Output Characteristics
• 5V, 10V and 15V Parametric Ratings
• Schmitt-Triggered Clock Inputs
• Meets All Requirements of JEDEC Tentative Stan-
dards No. 13B, “Standard Specifications for Descrip-
tion of “B” Series CMOS Device’s
Applications
CD4033BMS consists of a 5 stage Johnson decade counter
and an output decoder which converts the Johnson code to a 7
segment decoded output for driving one stage in a numerical
display.
This device is particularly advantageous in display applications
where low power dissipation and/or low package count is
important.
A high RESET signal clears the decade counter to its zero
count. The counter is advanced one count at the positive clock
signal transition if the CLOCK INHIBIT signal is low. Counter
advancement via the clock line is inhibited when the CLOCK
INHIBIT signal is high. The CLOCK INHIBIT signal can be used
as a negative-edge clock if the clock line is held high. Antilock
gating is provided on the JOHNSON counter, thus assuring
proper counting sequence. The CARRY-OUT (Cout) signal
completes one cycle every ten CLOCK INPUT cycles and is
used to clock the succeeding decade directly in a multi-decade
counting chain.
The seven decoded outputs (a, b, c, d, e, f, g) illuminate the
proper segments in a seven segment display device used for
representing the decimal numbers 0 to 9. The 7 segment out-
puts go high on selection.
• Decade Counting 7 Segment Decimal Display
• Frequency Division 7 Segment Decimal Displays
• Clocks, Watches, Timers (e.g. ÷ 60, ÷ 60, ÷12 Counter/
Display
• Counter/Display Driver For Meter Applications
Pinout
CD4033BMS
TOP VIEW
CLOCK 1
CLOCK INHIBIT 2
RIPPLE BLANKING IN 3
RIPPLE BLANKING OUT 4
CARRY OUT 5
f6
g7
VSS 8
16 VDD
15 RESET
14 LAMP TEST
13 c
12 b
11 e
10 a
9d
Functional Diagram
VDD
16
1
CLOCK
2
CLOCK
INHIBIT
15
RESET
14
LAMP
TEST
RIPPLE
BLK
IN
3
10 a
12 b
13 c
9d
11 e
6f
7g
8
VSS
5 CARRY OUT
4
RIPPLE
BLK
OUT
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-826
File Number 3301


Intersil Electronic Components Datasheet

CD4033BMS Datasheet

CMOS Decade Counter/Divider

No Preview Available !

CD4033BMS
The CD4033BMS has provisions for automatic blanking of
the non-significant zeros in a multi-digit decimal number
which results in an easily readable display consistent with
normal writing practice. For example, the number 0050.0700
in an eight digit display would be displayed as 50.07. Zero
suppression on the integer side is obtained by connecting
the RBI terminal of the CD4033BMS associated with the
most significant digit in the display to a low-level voltage and
connecting the RBO terminal of that stage to the RBI termi-
nal of the CD4033BMS in the next-lower significant position
in the display. This procedure is continued for each succeed-
ing CD4033BMS on the interger side of the display.
On the fraction side of the display the RBI of the
CD4033BMS associated with the least significant bit is con-
nected to a low-level voltage and the RBO of that
CD4033BMS is connected to the RBI terminal of the
CD4033BMS in the next more-significant-bit position. Again,
this procedure is continued for all CD4033BMS’s on the frac-
tion side of the display.
In a purely fractional number the zero immediately preceding
the decimal point can be displayed by connecting the RBI of
that stage to a high level voltage (instead of to the RBO of
the next more-significant-stage). For example: optional zero
0.7346. Likewise, the zero in a number such as 763.0 can
be displayed by connecting the RBI of the CD4033BMS
associated with it to a high-level voltage.
Ripple blanking of non-significant zeros provides an appre-
ciable savings in display power.
The CD4033BMS has a LAMP TEST input which, when con-
nected to a high-level voltage, overrides normal decoder
operation and enables a check to be made on possible dis-
play malfunctions by putting the seven outputs in the high
state.
The CD4033BMS are supplied in these 16 lead outline pack-
ages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4W
H2R
H6W
Logic Diagram
*LAMP TEST
14
DQ
CL
CL Q
15* R
DQ
CL
CL Q
R
DQ
CL
CL Q
R
DQ
CL
CL Q
R
DQ
CL
CL Q
R
RESET
COUT
(CLOCK ÷ 10)
5
10
a
12
b
1
*CLOCK
*CLOCK
INHIBIT 2
CL
3
*RBI
16
VDD
8
GND
*ALL INPUTS PROTECTED
BY CMOS INPUT
PROTECTION NETWORK
VDD
VSS
FIGURE 1. CD4033BMS
a
fg
e
d
b
SEGMENT
DESIGNATIONS
c
13
c
9
d
11
e
6
f
7
g
4
RBO
7-827


Part Number CD4033BMS
Description CMOS Decade Counter/Divider
Maker Intersil Corporation
PDF Download

CD4033BMS Datasheet PDF






Similar Datasheet

1 CD4033BMS CMOS Decade Counter/Divider
Intersil Corporation





Part Number Start With

0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R    S    T    U    V    W    X    Y    Z

Site map

Webmaste! click here

Contact us

Buy Components

Privacy Policy