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CD4073BMS - CMOS AND Gate

General Description

of ‘B’ Series CMOS Devices” B 2 J=A B 3 K=C

CD4073BMS, CD4081BMS and CD4082BMS AND gates provide the system designer with direct implementation of the AND function and supplement the existing family of CMOS gates.

Key Features

  • High-Voltage Types (20V Rating).
  • CD4073BMS Triple 3-Input AND Gate.
  • CD4081BMS Quad 2-Input AND Gate.
  • CD4082BMS Dual 4-Input AND Gate.
  • Medium Speed Operation: - tPLH, tPHL = 60ns (typ) at VDD = 10V.
  • 100% Tested for Quiescent Current at 20V.
  • Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC.
  • Noise Margin (Over Full Package Temperature Range): - 1V at VDD = 5V - 2V at VDD = 10V - 2.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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CD4073BMS, CD4081BMS CD4082BMS January 1993 CMOS AND Gate Pinout CD4073BMS TOP VIEW Features • High-Voltage Types (20V Rating) • CD4073BMS Triple 3-Input AND Gate • CD4081BMS Quad 2-Input AND Gate • CD4082BMS Dual 4-Input AND Gate • Medium Speed Operation: - tPLH, tPHL = 60ns (typ) at VDD = 10V • 100% Tested for Quiescent Current at 20V • Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC • Noise Margin (Over Full Package Temperature Range): - 1V at VDD = 5V - 2V at VDD = 10V - 2.