cmos dual 4-bit latch.
* High-Voltage Types (20-Volt Rating)
* Two Independent 4-Bit Latches
* Individual Master Reset for Each 4-Bit Latch
* 3-State Outputs with High-Impedance.
* Medium-Speed Operation: tPHL = tPLH = 70nS (Typ.) at VDD = 10V and CL = 50pF
* 100% Tested for Quiescent Curre.
of ‘B’ Series CMOS Devices"
Functional Diagram
OUTPUT DISABLE D0A Q0A 4-BIT LATCH Q1A 3-STATE OUTUTS Q2A Q3A
Applications
* Buffer Storage
* Holding Registers
* Data Storage and Multiplexing
D1A D2A D3A STROBE RESET OUTPUT DISABLE D0B .
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