HCTS30MS Datasheet | Intersil

Features - 3 Micron Radiation Hardened SOS CMOS - Total Dose 200K RAD (Si) - SEP Effective LET No Upsets: >100 MEV-cm2/mg - Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/ Bit-Day (Typ) - Dose Rate Survivability: >1 x - Dose Rate Upset >10 RAD (Si)/s RAD (Si)/s 20ns Pulse - Latch-Up Free Under Any Conditions - Military Temperature Range: -55o C to +125o C - Significant Power Reduction pared to LSTTL ICs - DC Operating Voltage Range: 4.5V to 5.5V - LSTTL Input patibility - VIL = 0.8V Max - VIH = VCC/2 Min - Input Current Levels Ii ≤ 5µA at VOL, VOH 14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) MIL-STD-1835 CDFP3-F14 TOP VIEW 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC NC H G NC NC Y Description The Intersil HCTS30MS is a Radiation Hardened 8-Input NAND Gate. A high on all input forces the output to a low state. The HCTS30MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. B C D E F GND Ordering Information PART NUMBER HCTS30DMSR HCTS30KMSR HCTS30D/Sample HCTS30K/Sample HCTS30HMSR TEMPERATURE RANGE -55o C to +125o C -55o C to +125o C +25o C +25o C +25o C SCREENING LEVEL Intersil Class S Equivalent Intersil Class S Equivalent Sample Sample Die PACKAGE 14 Lead SBDIP 14 Lead Ceramic Flatpack 14 Lead SBDIP 14 Lead Ceramic Flatpack Die CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://.intersil. or 407-727-9207 | Copyright © Intersil Corporation 1999 Spec Number File Number 518639 3056.1 HCTS30MS Functional Diagram A B C D Y E F G H TRUTH TABLE INPUTS A L X X X X X X X H B X L X X X X X X H C X X L X X X X X H D X X X L X X X X H E X X X X L X X X H F X X X X X L X X H G X X X X X X L X H H X X X X X X X L H OUTPUTS Y H H H H H H H H L NOTE: L = Logic Level Low, H = Logic level High, X = Don’t Care Spec Number 441 Specifications HCTS30MS Absolute Maximum Ratings Supply Voltage...