HI5828 d/a equivalent, dual high speed cmos d/a.
* Throughput Rate . . . . . . . . . . . . . . . . . . . . . . .125+MSPS
* Low Power . . . . 312mW at 5V, 46mW at 3V (at 60MSPS)
* Integral Linearity Error . ..
* Basestations (Cellular, WLL)
* Quadrature Modulation
* Wireless Communications Systems
Q48.7x7A 125MSPS 1.
PIN NO. 11, 19, 26 13, 24 28 PIN NAME AGND AVDD CLK Analog Ground. Analog Supply (+2.7V to +5.5V). Clock Input. The master and slave latches shown in the functional block diagram are simple D-latches. Input data to the DAC passes through the “master.
Image gallery
TAGS
Download (Size : 124.08KB)