HM-6514 Datasheet | Intersil

March 1997 1024 x 4 CMOS RAM Description The HM-6514 is a 1024 x 4 static CMOS RAM fabricated using self-aligned silicon gate technology. The device utilizes synchronous circuitry to achieve high performance and low power operation. On-chip latches are provided for addresses allowing efficient interfacing with microprocessor systems. The data output can be forced to a high impedance state for use in expanded memory arrays. Gated inputs allow lower operating current and also eliminate the need for pull up or pull down resistors. The HM-6514 is a fully static RAM and may be maintained in any state for an indefinite period of time. Data retention supply voltage and supply current are guaranteed over temperature. Features - Low Power Standby - - - . . . . 125µW Max - Low Power Operation - - . . . 35m W/MHz Max - Data Retention - - - - . . . at 2.0V Min - TTL patible Input/Output - mon Data Input/Output - Three-State Output - Standard JEDEC Pinout - Fast Access Time- - - . . . 120/200ns Max - 18 Pin Package for High Density - On-Chip Address Register - Gated Inputs - No Pull Up or Pull Down Resistors Required Ordering Information 120ns HM3-6514S-9 HM1-6514S-9 24502BVA 8102402VA 200ns HM3-6514B-9 HM1-6514B-9 8102404VA 300ns HM3-6514-9 HM1-6514-9 8102406VA HM4-6514-B TEMPERATURE RANGE -40o C to +85o C -40o C to +85o C -40o C to +85o C -55o C to +125o C PACKAGE PDIP CERDIP JAN# SMD# CLCC PKG. NO. E18.3 F18.3 F18.3 F18.3 J18.B J18.B Pinouts HM-6514 (PDIP, CERDIP) TOP VIEW A6 A5 A4 A3 A0 A1 A2 E GND 1 2 3 4 5 6 7 8 9 18 VCC 17 A7 16 A8 15 A9 14 DQ0 13 DQ1 12 DQ2 11 DQ3 10 W HM-6514 (CLCC) TOP VIEW A6 VCC 18...