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Intersil Electronic Components Datasheet

HM-6551 Datasheet

256 x 4 CMOS RAM

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HM-6551/883
March 1997
256 x 4 CMOS RAM
Features
Description
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• Low Power Standby . . . . . . . . . . . . . . . . . . . . 50µW Max
• Low Power Operation . . . . . . . . . . . . . 20mW/MHz Max
• Fast Access Time. . . . . . . . . . . . . . . . . . . . . . 220ns Max
• Data Retention . . . . . . . . . . . . . . . . . . . . . . . .at 2.0V Min
• TTL Compatible Input/Output
• High Output Drive - 1 TTL Load
• Internal Latched Chip Select
• High Noise Immunity
• On-Chip Address Register
• Latched Outputs
• Three-State Output
The HM-6551/883 is a 256 x 4 static CMOS RAM fabricated
using self-aligned silicon gate technology. Synchronous cir-
cuit design techniques are employed to achieve high perfor-
mance and low power operation. On chip latches are
provided for address and data outputs allowing efficient
interfacing with microprocessor systems. The data output
buffers can be forced to a high impedance state for use in
expanded memory arrays.
The HM-6551/883 is a fully static RAM and may be main-
tained in any state for an indefinite period of time. Data
retention supply voltage and supply current are guaranteed
over temperature.
Ordering Information
PACKAGE
CERDIP
TEMPERATURE RANGE
220ns
-55oC to +125oC
HM-6551B/883
300ns
HM1-6551/883
PKG. NO.
F22.4
Pinout
HM-6551/883 (CERDIP)
TOP VIEW
A3 1
A2 2
A1 3
A0 4
A5 5
A6 6
A7 7
GND 8
D0 9
Q0 10
D1 11
22 VCC
21 A4
20 W
19 S1
18 E
17 S2
16 Q3
15 D3
14 Q2
13 D2
12 Q1
PIN DESCRIPTION
A Address Input
E Chip Enable
W Write Enable
S Chip Select
D Data Input
Q Data Output
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
6-101
File Number 2988.1


Intersil Electronic Components Datasheet

HM-6551 Datasheet

256 x 4 CMOS RAM

No Preview Available !

Functional Diagram
HM-6551/883
A0 A
A1 LATCHED
5 GATED
A5
A6
ADDRESS
REGISTER A
ROW
DECODER
32
A7
32 x 32
MATRIX
5
D0
A
8 8 8 8D
Q
Q0
A
D1
A
D2
A
D3
A
GATED COLUMN
DECODER
AND DATA I/O
33
D DATA Q
D
OUTPUT
LATCHES
Q
DQ
L
Q1
A
Q2
A
Q3
A
E
W
L
S2 D SELECT Q
LATCH
S1
AA
LATCHED ADDRESS
REGISTER
A2 A3 A4
NOTES:
1. Select Latch: L Low Q = D and Q latches on rising edge of L.
2. Address Latches And Gated Decoders: Latch on falling edge of E and gate on falling edge of E.
3. All lines positive logic-active high.
4. Three-State Buffers: A high output active.
5. Data Latches: L High Q = D and Q latches on falling edge of L.
6-102



Part Number HM-6551
Description 256 x 4 CMOS RAM
Maker Intersil Corporation
Total Page 9 Pages
PDF Download

HM-6551 Datasheet PDF





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