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Intersil Electronic Components Datasheet

ID82C55A Datasheet

CMOS Programmable Peripheral Interface

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82C55A
June 1998
CMOS Programmable
Peripheral Interface
Features
Description
• Pin Compatible with NMOS 8255A
• 24 Programmable I/O Pins
• Fully TTL Compatible
• High Speed, No “Wait State” Operation with 5MHz and
8MHz 80C86 and 80C88
• Direct Bit Set/Reset Capability
• Enhanced Control Word Read Capability
• L7 Process
• 2.5mA Drive Capability on All I/O Ports
• Low Standby Power (ICCSB) . . . . . . . . . . . . . . . . .10µA
Ordering Information
PART NUMBERS
TEMPERATURE PKG.
5MHz
8MHz PACKAGE
RANGE
NO.
CP82C55A-5
IP82C55A-5
CP82C55A
0oC to 70oC
IP82C55A 40 Ld PDIP -40oC to 85oC
E40.6
E40.6
CS82C55A-5
IS82C55A-5
CS82C55A
0oC to 70oC
IS82C55A 44 Ld PLCC -40oC to 85oC
N44.65
N44.65
CD82C55A-5 CD82C55A
ID82C55A-5
ID82C55A
40 Ld
CERDIP
MD82C55A-5/B MD82C55A/B
0oC to 70oC
-40oC to 85oC
-55oC to 125oC
F40.6
F40.6
F40.6
8406601QA 8406602QA SMD#
F40.6
MR82C55A-5/B
MR82C55A/B
44 Pad
CLCC
-55oC to 125oC J44.A
8406601XA 8406602XA SMD#
J44.A
The Intersil 82C55A is a high performance CMOS version of
the industry standard 8255A and is manufactured using a
self-aligned silicon gate CMOS process (Scaled SAJI IV). It
is a general purpose programmable I/O device which may be
used with many different microprocessors. There are 24 I/O
pins which may be individually programmed in 2 groups of
12 and used in 3 major modes of operation. The high
performance and industry standard configuration of the
82C55A make it compatible with the 80C86, 80C88 and
other microprocessors.
Static CMOS circuit design insures low operating power. TTL
compatibility over the full military temperature range and bus
hold circuitry eliminate the need for pull-up resistors. The
Intersil advanced SAJI process results in performance equal
to or greater than existing functionally equivalent products at
a fraction of the power.
Pinouts
82C55A (DIP)
TOP VIEW
82C55A (CLCC)
TOP VIEW
PA3 1
PA2 2
PA1 3
PA0 4
RD 5
CS 6
GND 7
A1 8
A0 9
PC7 10
PC6 11
PC5 12
PC4 13
PC0 14
PC1 15
PC2 16
PC3 17
PB0 18
PB1 19
PB2 20
40 PA4
39 PA5
38 PA6
37 PA7
36 WR
35 RESET
34 D0
33 D1
32 D2
31 D3
30 D4
29 D5
28 D6
27 D7
26 VCC
25 PB7
24 PB6
23 PB5
22 PB4
21 PB3
6 5 4 3 2 1 44 43 42 41 40
GND 7
NC 8
A1 9
A0 10
PC7 11
PC6 12
PC5 13
PC4 14
PC0 15
PC1 16
PC2 17
39 NC
38 RESET
37 D0
36 D1
35 D2
34 D3
33 D4
32 D5
31 D6
30 D7
29 NC
18 19 20 21 22 23 24 25 26 27 28
CS
GND
A1
A0
PC7
NC
PC6
PC5
PC4
PC0
PC1
82C55A (PLCC)
TOP VIEW
6 5 4 3 2 1 44 43 42 41 40
7 39
8 38
9 37
10 36
11 35
12 34
13 33
14 32
15 31
16 30
17 29
18 1920 21 22 23 24 25 26 27 28
RESET
D0
D1
D2
D3
NC
D4
D5
D6
D7
VCC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
File Number 2969.2


Intersil Electronic Components Datasheet

ID82C55A Datasheet

CMOS Programmable Peripheral Interface

No Preview Available !

Pin Description
SYMBOL
VCC
PIN
NUMBER
26
GND
D0-D7
7
27-34
RESET
35
CS 6
RD 5
WR 36
A0-A1
8, 9
PA0-PA7
1-4, 37-40
PB0-PB7
PC0-PC7
18-25
10-17
Functional Diagram
82C55A
TYPE
I/O
I
I
I
I
I
I/O
I/O
I/O
DESCRIPTION
VCC: The +5V power supply pin. A 0.1µF capacitor between pins 26 and 7 is
recommended for decoupling.
GROUND
DATA BUS: The Data Bus lines are bidirectional three-state pins connected to the
system data bus.
RESET: A high on this input clears the control register and all ports (A, B, C) are set
to the input mode with the “Bus Hold” circuitry turned on.
CHIP SELECT: Chip select is an active low input used to enable the 82C55A onto the
Data Bus for CPU communications.
READ: Read is an active low input control signal used by the CPU to read status
information or data via the data bus.
WRITE: Write is an active low input control signal used by the CPU to load control
words and data into the 82C55A.
ADDRESS: These input signals, in conjunction with the RD and WR inputs, control
the selection of one of the three ports or the control word register. A0 and A1 are
normally connected to the least significant bits of the Address Bus A0, A1.
PORT A: 8-bit input and output port. Both bus hold high and bus hold low circuitry are
present on this port.
PORT B: 8-bit input and output port. Bus hold high circuitry is present on this port.
PORT C: 8-bit input and output port. Bus hold circuitry is present on this port.
POWER
SUPPLIES
+5V
GND
GROUP A
CONTROL
BI-DIRECTIONAL
DATA BUS
D7-D0
DATA BUS
BUFFER
RD
WR
A1
A0
RESET
CS
READ
WRITE
CONTROL
LOGIC
8-BIT
INTERNAL
DATA BUS
GROUP B
CONTROL
GROUP A
PORT A
(8)
GROUP A
PORT C
UPPER
(4)
GROUP B
PORT C
LOWER
(4)
GROUP B
PORT B
(8)
I/O
PA7-PA0
I/O
PC7-PC4
I/O
PC3-PC0
I/O
PB7-PB0
2


Part Number ID82C55A
Description CMOS Programmable Peripheral Interface
Maker Intersil Corporation
Total Page 26 Pages
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