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Intersil Electronic Components Datasheet

ID82C82 Datasheet

CMOS Octal Latching Bus Driver

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82C82
March 1997
CMOS Octal Latching Bus Driver
Features
Description
• Full Eight-Bit Parallel Latching Buffer
• Bipolar 8282 Compatible
• Three-State Noninverting Outputs
• Propagation Delay . . . . . . . . . . . . . . . . . . . . . 35ns Max.
• Gated Inputs:
- Reduce Operating Power
- Eliminate the Need for Pull-Up Resistors
• Single 5V Power Supply
• Low Power Operation . . . . . . . . . . . . . . . ICCSB = 10µA
• Operating Temperature Ranges
- C82C82 . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to +70oC
- I82C82 . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
- M82C82 . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
The Intersil 82C82 is a high performance CMOS Octal
Latching Buffer manufactured using a self-aligned silicon
gate CMOS process (Scaled SAJI IV). The 82C82 provides
an eight-bit parallel latch/buffer in a 20 pin package. The
active high strobe (STB) input allows transparent transfer of
data and latches data on the negative transition of this sig-
nal. The active low output enable (OE) permits simple inter-
face to state-of-the-art microprocessor systems.
Ordering Information
PART NUMBER
CP82C82
IP82C82
CS82C82
IS82C82
CD82C82
ID82C82
MD82C82/B
TEMP. RANGE
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
-55oC to +125oC
PACKAGE
20 Ld PDIP
20 Ld PLCC
20 Ld CERDIP
PKG. NO.
E20.3
N20.35
F20.3
8406701RA
MR82C82/B
SMD #
-55oC to +125oC 20 Pad CLCC J20.A
84067012A
SMD #
Pinouts
82C82 (PDIP, CERDIP)
TOP VIEW
82C82 (PLCC, CLCC)
TOP VIEW
DI0 1
DI1 2
DI2 3
DI3 4
DI4 5
DI5 6
DI6 7
DI7 8
OE 9
GND 10
20 VCC
19 DO0
18 DO1
17 DO2
16 DO3
15 DO4
14 DO5
13 DO6
12 DO7
11 STB
3 2 1 20 19
DI3 4
DI4 5
DI5 6
DI6 7
DI7 8
18 DO1
17 DO2
16 DO3
15 DO4
14 DO5
9 10 11 12 13
TRUTH TABLE
STB OE DI
DO
X H X Hi-Z
H LL L
H LH H
LX
H = Logic One
L = Logic Zero
X = Don’t Care
= Latched to Value of Last
Data
Hi-Z = High Impedance
= Neg. Transition
PIN NAMES
PIN
DI0-DI7
DO0-DO7
STB
OE
DESCRIPTION
Data Input Pins
Data Output Pins
Active High Strobe
Active Low Output
Enable
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
4-274
File Number 2975.1


Intersil Electronic Components Datasheet

ID82C82 Datasheet

CMOS Octal Latching Bus Driver

No Preview Available !

Functional Diagram
82C82
DIO D Q
CLK
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
STB
OE
Gated Inputs
During normal system operation of a latch, signals on the bus
at the device inputs will become high impedance or make
transitions unrelated to the operation of the latch. These unre-
lated input transitions switch the input circuitry and typically
cause an increase in power dissipation in CMOS devices by
creating a low resistance path between VCC and GND when
the signal is at or near the input switching threshold. Addition-
ally, if the driving signal becomes high impedance (“float” con-
dition), it could create an indeterminate logic state at the input
and cause a disruption in device operation.
The Intersil 82C8X Series of bus drivers eliminates these con-
ditions by turning off data inputs when data is latched (STB =
logic zero for the 82C82/83H) and when the device is disabled
(OE = logic one for 82C86H/87H). These gated inputs dis-
connect the input circuitry from the VCC and ground power
supply pins by turning off the upper P-channel and lower N-
channel (see Figures 1, 2). No new current flow from VCC to
GND occurs during input transitions and invalid logic states
from floating inputs are not transmitted. The next stage is held
to a valid logic level internal to the device.
DC input voltage levels can also cause an increase in ICC if
these input levels approach the minimum VIH or maximum
VIL conditions. This is due to the operation of the input cir-
cuitry in its linear operating region (partially conducting
state). The 82C8X series gated inputs mean that this condi-
tion will occur only during the time the device is in the trans
parent mode (STB = logic one). ICC remains below the max-
imum ICC standby specification of l0mA during the time
inputs are disabled, thereby, greatly reducing the average
power dissipation of the 82C8X series devices
Typical 82C82 System Example
In a typical 80C86/88 system, the 82C82 is used to latch
multiplexed addresses and the STB input is driven by ALE
(Address Latch Enable) (see Figure 3). The high pulse width
of ALE is approximately 100ns with a bus cycle time of
800ns (80C86/88 at 5MHz). The 82C82 inputs are active
only 12.5% of the bus cycle time. Average power dissipation
related to input transitioning is reduced by this factor also.
STB
DATA IN
VCC
P
N
VCC
P
P
INTERNAL
DATA
N
N
OE
DATA IN
VCC
P
N
VCC
P
P
INTERNAL
DATA
N
N
FIGURE 16. 82C82/83H
FIGURE 17. 82C86H/87H GATED INPUTS
4-275


Part Number ID82C82
Description CMOS Octal Latching Bus Driver
Maker Intersil Corporation
Total Page 7 Pages
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