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Intersil Electronic Components Datasheet

ID82C83H Datasheet

CMOS Octal Latching Inverting Bus Driver

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82C83H
March 1997
CMOS Octal Latching Inverting Bus Driver
Features
• Full 8-Bit Parallel Latching Buffer
• Bipolar 8283 Compatible
• Three-State Inverting Outputs
• Propagation Delay . . . . . . . . . . . . . . . . . . . . . . 25ns Max
• Gated Inputs
- Reduce Operating Power
- Eliminate the Need for Pull-Up Resistors
• Single 5V Power Supply
• Low Power Operation
- ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
• Operating Temperature Ranges
- C82C83H . . . . . . . . . . . . . . . . . . . . . . . . .0oC to +70oC
- I82C83H . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
- M82C83H . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
Description
The Intersil 82C83H is a high performance CMOS Octal
Latching Buffer manufactured using a self-aligned silicon gate
CMOS process (Scaled SAJI IV). The 82C83H provides an 8-
bit parallel latch/buffer in a 20 lead pin package. The active
high strobe (STB) input allows transparent transfer of data
and latches data on the negative transition of this signal. The
active low output enable (OE) permits simple interface to
microprocessor systems. The 82C83H provides inverted data
at the outputs.
Ordering Information
PART NO.
CP82C83H
IP82C83H
CS82C83H
IS82C83H
CD82C83H
ID82C83H
MD82C83H/B
8406702RA
MR82C83H/B
84067022A
PACKAGE
20 Ld PDIP
20 Ld PLCC
20 Ld CERDIP
SMD#
20 Pad CLCC
SMD#
TEMP RANGE
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-55oC to +125oC
-55oC to +125oC
-55oC to +125oC
PKG. NO
E20.3
E20.3
N20.35
N20.35
F20.3
F20.3
F20.3
F20.3
J20.A
J20.A
Pinouts
82C83H (PDIP, CERDIP)
TOP VIEW
82C83H (PLCC, CLCC)
TOP VIEW
DI0 1
DI1 2
DI2 3
DI3 4
DI4 5
DI5 6
DI6 7
DI7 8
OE 9
GND 10
20 VCC
19 DO0
18 DO1
17 DO2
16 DO3
15 DO4
14 DO5
13 DO6
12 DO7
11 STB
3 2 1 20 19
DI3 4
DI4 5
DI5 6
DI6 7
DI7 8
18 DO1
17 DO2
16 DO3
15 DO4
14 DO5
9 10 11 12 13
STB
X
H
H
H = Logic One
L = Logic Zero
X = Don‘t Care
TRUTH TABLE
OE DI DO
H X HI-Z
L LH
LHL
LX
HI-Z = High Impedance
= Negative Transition
= Latched to Value of Last
Data
PIN
DI0 - DI7
DO0 - DO7
STB
OE
PIN NAMES
DESCRIPTION
Data Input Pins
Data Output Pins
Active High Strobe
Active Low Output Enable
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
4-281
File Number 2971.1


Intersil Electronic Components Datasheet

ID82C83H Datasheet

CMOS Octal Latching Inverting Bus Driver

No Preview Available !

82C83H
Functional Diagram
DQ
DI0 CLK
DI1
DI2
DI3
DI4
DI5
DI6
DI7
STB
state). The 82C8X series gated inputs mean that this condi-
tion will occur only during the time the device is in the trans-
parent mode (STB = logic one). ICC remains below the
DO0 maximum ICC standby specification of 10µA during the time
inputs are disabled, thereby greatly reducing the average
power dissipation of the 82C8X series devices.
DO1
DO2
DO3
DO4
DO5
DO6
DO7
OE
OE
DATA IN
VCC
P
N
VCC
P
P
INTERNAL
DATA
N
N
Gated Inputs
During normal system operation of a latch, signals on the
bus at the device inputs will become high impedance or
make transitions unrelated to the operation of the latch.
These unrelated input transitions switch the input circuitry
and typically cause an increase in power dissipation in
CMOS devices by creating a low resistance path between
VCC and GND when the signal is at or near the input switch-
ing threshold. Additionally, if the driving signal becomes high
impedance (``float'' condition), it could create an indetermi-
nate logic state at the inputs and cause a disruption in
device operation.
The Intersil 82C8X series of bus drivers eliminates these
conditions by turning off data inputs when data is latched
(STB = logic zero for the 82C82/83H) and when the device is
disabled (OE = logic one for the 82C86H/87H). These gated
inputs disconnect the input circuitry from the VCC and
ground power supply pins by turning off the upper P-channel
and lower N-channel (See Figures 1 and 2). No current flow
from VCC to GND occurs during input transitions and invalid
logic states from floating inputs are not transmitted. The next
stage is held to a valid logic level internal to the device.
STB
DATA IN
VCC
P
N
VCC
P
P
INTERNAL
DATA
N
N
FIGURE 1. 82C82/83H
FIGURE 2. 82C86H/87H GATED INPUTS
Decoupling Capacitors
The transient current required to charge and discharge the
300pF load capacitance specified in the 82C83H data sheet
is determined by
I = CL (dv/dt)
Assuming that all outputs change state at the same time and
that dv/dt is constant;
I = CL(--V-----C----C------×-----8t-R--0------t-p-F---e----r--c----e----n---t---)
(EQ. 1)
where tR = 20ns, VCC = 5.0V, CL = 300pF on each eight out-
puts.
I = (8 x 300 x 10-12) x (5.0V x 0.8)/(20 x 10-9) = 480mA
This current spike may cause a large negative voltage spike on
VCC which could cause improper operation of the device. To fil-
ter out this noise, it is recommended that a 0.1µF ceramic disc
capacitor be placed between VCC and GND at each device,
with placement being as near to the device as possible.
ALE
MULTI-
PLEXED
BUS
ICC
ADDRESS
ADDRESS
STB
DATA IN
VCC
P
N
VCC
P
P
INTERNAL
DATA
N
D.C. input voltage levels can also cause an increase in ICC if
these input levels approach the minimum VIH or maximum
VIL conditions. This is due to the operation of the input cir-
cuitry in its linear operating region (partially conducting
N
FIGURE 3. SYSTEM EFFECTS OF GATED INPUTS
4-282


Part Number ID82C83H
Description CMOS Octal Latching Inverting Bus Driver
Maker Intersil Corporation
Total Page 6 Pages
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