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Intersil Electronic Components Datasheet

ID82C88 Datasheet

CMOS Bus Controller

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82C88
March 1997
CMOS Bus Controller
Features
Description
• Compatible with Bipolar 8288
• Performance Compatible with:
- 80C86/80C88 . . . . . . . . . . . . . . . . . . . . . . . . . .(5/8MHz)
- 80186/80188 . . . . . . . . . . . . . . . . . . . . . . . . . .(6/8MHz)
- 8086/8088 . . . . . . . . . . . . . . . . . . . . . . . . . . . .(5/8MHz)
- 8089
• Provides Advanced Commands for Multi-Master
Busses
• Three-State Command Outputs
• Bipolar Drive Capability
• Scaled SAJI IV CMOS Process
• Single 5V Power Supply
• Low Power Operation
- ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10µA (Max)
- ICCOP . . . . . . . . . . . . . . . . . . . . . . . . .1mA/MHz (Max)
• Operating Temperature Ranges
- C82C88 . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to +70oC
- I82C88 . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
- M82C88 . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
The Intersil 82C88 is a high performance CMOS Bus Con-
troller manufactured using a self-aligned silicon gate CMOS
process (Scaled SAJI IV). The 82C88 provides the control
and command timing signals for 80C86, 80C88, 8086, 8088,
8089, 80186, and 80188 based systems. The high output
drive capability of the 82C88 eliminates the need for addi-
tional bus drivers.
Static CMOS circuit design insures low operating power. The
Intersil advanced SAJI process results in performance equal
to or greater than existing equivalent products at a significant
power savings.
Ordering Information
PART NUMBER
CP82C88
CP82C88-10
IP82C88
CS82C88
IS82C88
CD82C88
ID82C88
MD82C88/B
8406901RA
MR82C88/B
84069012A
PACKAGE
20 Ld PDIP
20 Ld
PLCC
20 Ld
CERDIP
SMD#
20 Pad
CLCC
SMD#
TEMPERATURE
RANGE
0oC to +70oC
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
-55oC to +125oC
-55oC to +125oC
PKG.
NO.
E20.3
E20.3
E20.3
N20.35
N20.35
F20.3
F20.3
F20.3
F20.3
J20.A
J20.A
Pinouts
20 LEAD PDIP, CERDIP
TOP VIEW
IOB 1
CLK 2
S1 3
DT/ R 4
ALE 5
AEN 6
MRDC 7
AMWC 8
MWTC 9
GND 10
20 VCC
19 S0
18 S2
17 MCE/PDEN
16 DEN
15 CEN
14 INTA
13 IORC
12 AIOWC
11 IOWC
20 LEAD PLCC, CLCC
TOP VIEW
3 2 1 20 19
DT/ R 4
ALE 5
AEN 6
18 S2
17 MCE/PDEN
16 DEN
MRDC 7
15 CEN
AMWC 8
14 INTA
9 10 11 12 13
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
4-333
File Number 2979.1


Intersil Electronic Components Datasheet

ID82C88 Datasheet

CMOS Bus Controller

No Preview Available !

Functional Diagram
S0
S1
S2
CONTROL
INPUT
CLK
AEN
CEN
IOB
STATUS
DECODER
CONTROL
LOGIC
82C88
COMMAND
SIGNAL
GENERATOR
CONTROL
SIGNAL
GENERATOR
MRDC
MWTC
AMWC
IORC
IOWC
AIOWC
INTA
DT/R
DEN
MCE/PDEN
ALE
MULTIBUSTM
COMMAND
SIGNALS
ADDRESS LATCH,
DATA TRANSCEIVER,
AND INTERRUPT
CONTROL SIGNALS
VCC
GND
Pin Description
PIN
SYMBOL NUMBER TYPE
DESCRIPTION
VCC
GND
20
10
VCC: The +5V power supply pin. A 0.1µF capacitor between pins 10 and 20 is recommended for decoupling.
GROUND.
S0, S1, S2 19, 3, 18
I STATUS INPUT PINS: These pins are the input pins from the 80C86, 80C88,8086/88, 8089 processors.
The 82C88 decodes these inputs to generate command and control signals at the appropriate time.
When Status pins are not in use (passive), command outputs are held HIGH (See Table1).
CLK 2 I CLOCK: This is a CMOS compatible input which receives a clock signal from the 82C84A or 82C85 clock
generator and serves to establish when command/control signals are generated.
ALE 5 O ADDRESS LATCH ENABLE: This signal serves to strobe an address into the address latches. This sig-
nal is active HIGH and latching occurs on the falling (HIGH to LOW) transition. ALE is intended for use
with transparent D type latches, such as the 82C82 and 82C83H.
DEN
16 O DATA ENABLE: This signal serves to enable data transceivers onto either the local or system data bus.
This signal is active HIGH.
DT/R
4 O DATA TRANSMIT/RECEIVE: This signal establishes the direction of data flow through the transceivers.
A HIGH on this line indicates Transmit (write to I/O or memory) and a LOW indicates Receive (read from
I/O or memory).
AEN 6 I ADDRESS ENABLE: AEN enables command outputs of the 82C88 Bus Controller a minimum of 110ns
(250ns maximum) after it becomes active (LOW). AEN going inactive immediately three-states the com-
mand output drivers. AEN does not affect the I/O command lines if the 82C88 is in the I/O Bus mode
(IOB tied HIGH).
CEN 15 I COMMAND ENABLE: When this signal is LOW all 82C88 command outputs and the DEN and PDEN con-
trol outputs are forced to their Inactive state. When this signal is HIGH, these same outputs are enabled.
IOB 1 I INPUT/OUTPUT BUS MODE: When the IOB pin is strapped HIGH, the 82C88 functions in the I/O Bus
mode. When it is strapped LOW, the 82C88 functions in the System Bus mode (See I/O Bus and System
Bus sections).
Intel™ is a Registered Trademark of Intel Corporation
4-334


Part Number ID82C88
Description CMOS Bus Controller
Maker Intersil Corporation
Total Page 10 Pages
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