SBDIP Description
The CDP1802A/3 High-Reliability LSI CMOS 8-bit register oriented Central-Processing Unit (CPU) is designed for use as a general purpose puting or control element in a wide range of stored-program systems or products. The CDP1802A/3 includes all of the circuits required for fetching, interpreting, and executing instructions which have been stored in standard types of memories. Extensive input/output (I/O) control.
SBDIP Key Features
- For Use In Aerospace, Military, and Critical Industrial Equipment
- Minimum Instruction Fetch-Execute Time of 4.5µs (Maximum Clock Frequency of 3.6MHz) at VDD = 5V, TA = +25oC
- Operation Over the Full Military Temperature Range
- 55oC to +125oC
- Any bination of Standard RAM and ROM Up to 65,536 Bytes
- 8-Bit Parallel Organization With Bidirectional Data Bus and Multiplexed Address Bus
- 16 x 16 Matrix of Registers for Use as Multiple Program Counters, Data Pointers, or Data Registers
- On-Chip DMA, Interrupt, and Flag Inputs
- High Noise Immunity
- 30% of VDD