Name and Function
I/O PORT A, PINS 0-3: Lower nibble of an 8-bit data output latch buffer
and an 8-bit data input latch.
I READ CONTROL: This input is low during CPU read operations.
I CHIP SELECT: A low on this input enables the 82C55A to respond
to RD and WR signals RD and WR are ignored otherwise.
I ADDRESS: These input signals in conjunction RD and WR control
the selection of one of the three ports or the control word registers.
RD WR CS Input Operation (Read)
0 0 0 1 0 Port A - Data Bus
0 1 0 1 0 Port B - Data Bus
1 0 0 1 0 Port C - Data Bus
1 1 0 1 0 Control Word - Data Bus
Output Operation (Write)
0 0 1 0 0 Data Bus - Port A
0 1 1 0 0 Data Bus - Port B
1 0 1 0 0 Data Bus - Port C
1 1 1 0 0 Data Bus – Control
x x x x 1 Data Bus-3-State
x x 1 1 0 Data Bus-3-State
I/O PORT C, PINS 4-7: Upper nibble of an 8-bit data output latch/buffer
and an 8-bit data input buffer (no latch for input). This port can be
divided into two 4-bit ports under the mode control. Each 4-bit port
contains a 4-bit latch and it can be used for the control signal outputs
and status signal inputs in conjunction with ports A and B.
I/O PORT C, PINS 0-3: Lower nibble of Port C.
I/O PORT B, PINS 0-7: An 8-bit data output latch/buffer and an 8-bit
data input buffer
SYSTEM POWER: +5V Power Supply
I/O DATA BUS: Bi-directional, tri-state data bus lines, connected to
system data bus
I RESET: A high on this input clears the control register and all ports
are set to the input mode
I WRITE CONTROL: This input is low during CPU write operations
I/O PORT A PINS 4-7: Upper nibble of an 8-bit data output latch/buffer
and an 8-bit data input latch
datasheet pdf - http://www.DataSheet4U.net/