* NB is low. ENB should be kept normally low and pulsed high to transfer data to the latches. CLK Shift Register Clock (PDIP, SOG
* Pin 11, SSOP
* Pin 16) A low
* to
* high transition on this input shifts data from the serial data input into the shift registers. COMPONENT
ML145159 Datasheet (674.68 KB)
ML145159
LANSDALE Semiconductor
674.68 KB
Serial-input pll frequency synthesizer.
www.DataSheet4U.com ML145159 Serial-Input PLL Frequency Synthesizer with Analog Phase Detector INTERFACES WITH DUAL MODULUS PRESCALERS Legac.
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