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LOGIC Devices Incorporated

L29C525JC15 Datasheet Preview

L29C525JC15 Datasheet

Dual Pipeline Register

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DEVICES INCORPORATED
DEVICES INCORPORATED
L29C525
Dual PLip2el9inCe R5eg2is5ter
Dual Pipeline Register
FEATURES
DESCRIPTION
u Dual 8-Deep Pipeline Register
u Configurable to Single 16-Deep
u Low Power CMOS Technology
u Replaces AMD Am29525
u Load, Shift, and Hold Instructions
u Separate Data In and Data Out Pins
u Three-State Outputs
u Package Styles Available:
• 28-pin Plastic DIP
• 28-pin Plastic LCC, J-Lead
The L29C525 is a high-speed, low
power CMOS pipeline register. It is
pin-for-pin compatible with the AMD
Am29525. The L29C525 can be
configured as two independent 8-level
pipelines or as a single 16-level
pipeline. The configuration imple-
mented is determined by the instruc-
tion code (I1-0) as shown in Table 2.
The I1-0 instruction code controls the
internal routing of data and loading of
each register. For instruction I1-0 = 00
(Push A and B), data applied at the
D7-0 inputs is latched into register A0
on the rising edge of CLK. The
contents of A0 simultaneously move
to register A1, A1 moves to A2, and so
on. The contents of register A7 are
wrapped back to register B0. The
registers on the B side are similarly
shifted, with the contents of register
B7 lost.
Instruction I1-0 = 01 (Push B) acts
similarly to the Push A and B
instruction, except that only the B side
registers are shifted. The input data is
applied to register B0, and the
contents of register B7 are lost. The
contents of the A side registers are
unaffected. Instruction I1-0 = 10 (Push
A) is identical to the Push B
instruction, except that the A side
registers are shifted and the B side
registers are unaffected.
Instruction I1-0 = 11 (Hold) causes no
internal data movement. It is equiva-
lent to preventing the application of a
clock edge to any internal register.
The contents of any of the registers is
selectable at the output through the
use of the S3-0 control inputs. The
independence of the I and S control
lines allows simultaneous reading and
writing. Encoding for the S3-0 controls
is given in Table 3.
L29C525 BLOCK DIAGRAM
D7-0
I1-0
CLK
8
2
A0
A1
A2
A3
A4
A5
A6
A7
Y7-0
B0 8
B1
OE
B2
B3
B4
B5
B6
B7
S3-0
4
Pipeline Registers
1 03/23/2000–LDS.29C525-G




LOGIC Devices Incorporated

L29C525JC15 Datasheet Preview

L29C525JC15 Datasheet

Dual Pipeline Register

No Preview Available !

DEVICES INCORPORATED
TABLE 1. REGISTER LOAD OPERATIONS
Single 16 Level
Push A and B
Push B
A0 B0
A1 B1
A2 B2
A3 B3
A4 B4
A5 B5
A6 B6
A7 B7
HOLD
A0
A1
A2
A3
A4
A5
A6
A7
B0
B1
B2
B3
B4
B5
B6
B7
L29C525
Dual Pipeline Register
Dual 8 Level
Push A
HOLD
A0 B0
A1 B1
A2 B2
A3 B3
A4 B4
A5 B5
A6 B6
A7 B7
Hold All Registers
HOLD
A0
A1
A2
A3
A4
A5
A6
A7
HOLD
B0
B1
B2
B3
B4
B5
B6
B7
TABLE 2. INSTRUCTION SET
Inputs
Mnemonics I1
I0 Description
Shift
0 0 Push A and B
LDB 0 1 Push B
LDA 1 0 Push A
HLD
1 1 Hold All Registers
TABLE 3. OUTPUT SELECT
S3 S2 S1 S0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Y7-0
A0
A1
A2
A3
A4
A5
A6
A7
B0
B1
B2
B3
B4
B5
B6
B7
Pipeline Registers
2 03/27/2000–LDS.29C525-G


Part Number L29C525JC15
Description Dual Pipeline Register
Maker LOGIC Devices Incorporated
Total Page 6 Pages
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