MR4010 Datasheet Superscalar Microprocessor

Manufacturer: LSI Logic

Overview: MiniRISC™ MR4010 Superscalar Microprocessor Reference Device www.DataSheet4U.

MR4010 superscalar microprocessor by LSI Logic - Datasheet Preview

Datasheet Details

Part number	MR4010
Manufacturer	LSI Logic
File Size	451.78 KB
Description	Superscalar Microprocessor
Download	MR4010 Download (PDF)

General Description

s 4.1 SCbus Interface 4.2 External Buffering for SCbus Signals 4.3 CW4010 Shell Interface 4.4 Mbus Interface 4.5 Lbus Interface 4.6 Phase-Locked Loop (PLL) Clock Signals 4.6 Test Signals 4.7 CW4010 Core Monitor Signals PLL Circuit System Conﬁguration 6.1 CW4010 CCC Register 6.2 Lbus Controller Registers MR4010 Memory Map CW4010 Instruction Set Summary DRAM Controller and Memory Bus 9.1 DRAM Types and Available DRAM Address Area 9.2 Memory Interface 9.3 Address Bit Assignment 9.4 DRAM Modes and Programmable Conﬁgurations 9.5 DRAM Refresh 9.6 DRAM Commands 9.7 Initializing the DRAM and Programming the Mode 7 9 10 12 12 12 13 13 14 21 24 26 28 31 32 33 36 37 37 41 42 43 55 55 56 58 59 67 69 November 1996 Copyright © 1996 by LSI Logic Corporation.

1 www.DataSheet4U.com 10 11 12 13 14 Register 9.8 DRAM Transactions Local I/O bus and SCbus/Lbus Converter Module 10.1 Lbus

Key Features

MR4010 Functional Blocks 2.1 CW4010 Shell 2.2 Synchronous DRAM Controller (DRAMC) 2.3 SCbus to Local I/O Bus (Lbus) Controller (SCLC) 2.4 PLL Clock Circuit MR4010 Programming Model Signal.

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