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ISPGAL22V10 - In-System Programmable E2CMOS PLD

Description

PIN CONFIGURATION The ispGAL22V10, at 7.5ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the industry's first in-system programmable 22V10 device.

Features

  • IN-SYSTEM.

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Datasheet preview – ISPGAL22V10

Datasheet Details

Part number ISPGAL22V10
Manufacturer Lattice Semiconductor
File Size 280.40 KB
Description In-System Programmable E2CMOS PLD
Datasheet download datasheet ISPGAL22V10 Datasheet
Additional preview pages of the ISPGAL22V10 datasheet.

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Full PDF Text Transcription

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Specifications ispGAL22V10 ispGAL22V10 In-System Programmable E2CMOS PLD Generic Array Logic™ FEATURES • IN-SYSTEM PROGRAMMABLE™ (5-V ONLY) — 4-Wire Serial Programming Interface — Minimum 10,000 Program/Erase Cycles — Built-in Pull-Down on SDI Pin Eliminates Discrete Resistor on Board (ispGAL22V10C Only) • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — 7.
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