ISPLSI5512VE Datasheet | Lattice Semiconductor

isp LSI ® 5512VE In-System Programmable 3.3V Super WIDE™ High Density PLD Features - Second Generation Super WIDE HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC DEVICE - 3.3V Power Supply - User Selectable 3.3V/2.5V I/O - 24000 PLD Gates / 512 Macrocells - Up to 256 I/O Pins - 512 Registers - High-Speed Global Interconnect - Super WIDE Generic Logic Block (32 Macrocells) for Optimum Performance - Super WIDE Input Gating (68 Inputs) for Fast Counters, State Machines, Address Decoders, etc. - PCB Efficient Ball Grid Array (BGA) Package Options - Interfaces with Standard 5V TTL Devices - HIGH PERFORMANCE E2CMOS® TECHNOLOGY - fmax = 155 MHz Maximum Operating Frequency - tpd = 6.5 ns Propagation Delay - TTL/3.3V/2.5V patible Input Thresholds and Output Levels - Electrically Erasable and Reprogrammable - Non-Volatile - Programmable Speed/Power Logic Path Optimization - IN-SYSTEM PROGRAMMABLE - Increased Manufacturing Yields, Reduced Time-to Market, and Improved Product Quality - Reprogram Soldered Devices for Faster Debugging - 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND 3.3V IN-SYSTEM PROGRAMMABLE - ARCHITECTURE Features - Enhanced Pin-Locking Architecture with Single Level Global Routing Pool and Super WIDE GLBs - Wrap Around Product Term Sharing Array Supports up to 35 Product Terms Per Macrocell - Macrocells Support Concurrent binatorial and Registered Functions - Macrocell Registers Feature Multiple Control Options Including Set, Reset and Clock...