Datasheet4U Logo Datasheet4U.com

ISPLSI5512VE - High Density PLD

Description

The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs.

Outputs from the GLBs drive the Global Routing Pool (GRP) between the GLBs.

Features

  • Second Generation SuperWIDE HIGH.

📥 Download Datasheet

Datasheet preview – ISPLSI5512VE

Datasheet Details

Part number ISPLSI5512VE
Manufacturer Lattice Semiconductor
File Size 263.94 KB
Description High Density PLD
Datasheet download datasheet ISPLSI5512VE Datasheet
Additional preview pages of the ISPLSI5512VE datasheet.

📁 Similar Datasheet

  • ISP0912 - Bluetooth Low Energy Module (Insight SiP)
  • ISP091201 - Bluetooth Low Energy Module (Insight SiP)
  • ISP1040B - Intelligent SCSI Processor (QLogic Corporation)
  • ISP1040B - SCSI I/O Processor (Qlogic)
  • ISP1040C - Intelligent SCSI Processor (QLogic Corporation)
  • ISP1102 - Advanced Universal Serial Bus transceiver (NXP)
  • ISP1102BS - Advanced Universal Serial Bus transceiver (NXP)
  • ISP1102W - Advanced Universal Serial Bus transceiver (NXP)
  • ISP1103 - Universal Serial Bus transceiver (NXP)
  • ISP1103D - Universal Serial Bus transceiver (NXP)
Other Datasheets by Lattice Semiconductor
  • ISPLSI5512VA - In-System Programmable High Density PLD
  • ISPLSI5128VE - In-System Programmable 3.3V SuperWIDE High Density PLD
  • ISPLSI5256VA - In-System Programmable 3.3V SuperWIDE High Density PLD
  • ISPLSI5256VE - In-System Programmable 3.3V SuperWIDE High Density PLD
  • ISPLSI5384VA - In-System Programmable High Density PLD
  • ispLSI1016 - In-System Programmable High Density PLD
  • ISpLSI1016-883 - In-System Programmable High Density PLD
  • ISPLSI1016E - In-System Programmable High Density PLD

Full PDF Text Transcription

Click to expand full text
ispLSI ® 5512VE In-System Programmable 3.3V SuperWIDE™ High Density PLD Features • Second Generation SuperWIDE HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC DEVICE — 3.3V Power Supply — User Selectable 3.3V/2.5V I/O — 24000 PLD Gates / 512 Macrocells — Up to 256 I/O Pins — 512 Registers — High-Speed Global Interconnect — SuperWIDE Generic Logic Block (32 Macrocells) for Optimum Performance — SuperWIDE Input Gating (68 Inputs) for Fast Counters, State Machines, Address Decoders, etc. — PCB Efficient Ball Grid Array (BGA) Package Options — Interfaces with Standard 5V TTL Devices • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 155 MHz Maximum Operating Frequency — tpd = 6.5 ns Propagation Delay — TTL/3.3V/2.
Published: |