14-Bit, 130Msps ADC
n Sample Rate: 130Msps
n 77.1dBFS Noise Floor
n 98dB SFDR
n SFDR >81dB at 250MHz (1.5VP-P Input Range)
n PGA Front End (2.25VP-P or 1.5VP-P Input Range)
n 700MHz Full Power Bandwidth S/H
n Optional Internal Dither
n Optional Data Output Randomizer
n LVDS or CMOS Outputs
n Single 3.3V Supply
n Power Dissipation: 1.32W
n Clock Duty Cycle Stabilizer
n Pin Compatible 16-Bit Version
130Msps: LTC2208 (16-Bit)
n 64-Pin (9mm × 9mm) QFN Package
n Cellular Base Stations
n Spectrum Analysis
n Imaging Systems
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
The LTC®2208-14 is a 130Msps, sampling 14-bit A/D
converter designed for digitizing high frequency, wide
dynamic range signals with input frequencies up to
700MHz. The input range of the ADC can be optimized
with the PGA front end.
The LTC2208-14 is perfect for demanding communications
applications, with AC performance that includes 77.1dBFS
Noise Floor and 98dB spurious free dynamic range (SFDR).
Ultralow jitter of 70fsRMS allows undersampling of high
input frequencies with excellent noise performance.
Maximum DC specs include ±1.5LSB INL, ±0.5LSB DNL
(no missing codes).
The digital output can be either differential LVDS or
single-ended CMOS. There are two format options for the
CMOS outputs: a single bus running at the full data rate or
demultiplexed buses running at half data rate. A separate
output power supply allows the CMOS output swing to
range from 0.5V to 3.6V.
The ENC+ and ENC– inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL or
CMOS inputs. An optional clock duty cycle stabilizer al-
lows high performance at full speed with a wide range of
clock duty cycles.
ENC + ENC –
PGA SHDN DITH MODE LVDS RAND
ADC CONTROL INPUTS
0.5V TO 3.6V
32k Point FFT, fIN = 15.11MHz,
–1dB, PGA = 0, RAND “On”,
10 20 30 40 50 60