DIE CROSS REFERENCE
7 2. +IN
2 3. –IN
5. LATCH ENABLE
6 6. GND
*DWF = DICE in wafer form.
7. Q OUT
8. Q OUT
56mils × 58mils
Backside Connection is V–
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DICE ELECTRICAL TEST LIMITS
TA = 25°C. V+ = 5V, V– = –5V, VOUT(Q) = 1.4V, VLATCH = 0V, unless otherwise speciﬁed.
MIN MAX UNITS
Input Offset Voltage
Input Offset Current
Input Bias Current
Input Voltage Range
Common Mode Rejection
Supply Voltage Rejection
Small-Signal Voltage Gain
Output High Voltage
Output Low Voltage
Positive Supply Current
Negative Supply Current
RS ≤ 100Ω (Note 1)
Single 5V Supply (Note 3)
–3.75V ≤ VCM ≤ 3.5V
Positive Supply 4.6V ≤ V+ ≤5.4V
Negative Supply –7V ≤ V– ≤ –2V
1V ≤ VOUT ≤ 2V
V+ ≥ 4.6V, IOUT = 1mA
IOUT = 10mA
ISINK = 4mA
VIH Latch Pin High Input Voltage
wwwVI.LDataSheet4U.Lcaotcmh Pin Low Input Voltage
IIL Latch Pin Current
VLATCH = 0V
Note 1: Input offset voltage is deﬁned as the average of the two voltages
measured by forcing ﬁrst one output, then the other to 1.4V. Input offset
current is deﬁned in the same way.
Note 2: Input bias current (IB) is deﬁned as the average of the two input
Note 3: Input voltage range is guaranteed in part by CMRR testing and
in part by design and characterization. See the LT1016 data sheet for
discussion of input voltage range for supplies other than ±5V or 5V.
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.