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MACRONIX

MX25U6473F Datasheet Preview

MX25U6473F Datasheet

FLASH MEMORY

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MX25U6473F
MX25U6473F
1.8V, 64M-BIT [x 1/x 2/x 4]
CMOS MXSMIO® (SERIAL MULTI I/O)
FLASH MEMORY
Key Features
• Multi I/O Support - Single I/O, Dual I/O and Quad I/O
• Auto Erase and Auto Program Algorithms
• Program Suspend/Resume & Erase Suspend/Resume
• Permanently fixed QE bit, QE=1; and 4 I/O mode is enabled
P/N: PM2204
REV. 1.0, DEC. 31, 2014
1




MACRONIX

MX25U6473F Datasheet Preview

MX25U6473F Datasheet

FLASH MEMORY

No Preview Available !

MX25U6473F
Contents
1. FEATURES............................................................................................................................................................... 4
2. GENERAL DESCRIPTION...................................................................................................................................... 6
Table 1. Additional Feature...........................................................................................................................7
3. PIN CONFIGURATIONS .......................................................................................................................................... 8
4. PIN DESCRIPTION................................................................................................................................................... 8
5. BLOCK DIAGRAM.................................................................................................................................................... 9
6. DATA PROTECTION............................................................................................................................................... 10
Table 2. Protected Area Sizes.................................................................................................................... 11
Table 3. 4K-bit Secured OTP Definition.....................................................................................................12
7. MEMORY ORGANIZATION.................................................................................................................................... 13
Table 4. Memory Organization...................................................................................................................13
8. DEVICE OPERATION............................................................................................................................................. 14
8-1. Quad Peripheral Interface (QPI) Read Mode........................................................................................... 16
9. COMMAND DESCRIPTION.................................................................................................................................... 17
Table 5. Command Set...............................................................................................................................17
9-1. Write Enable (WREN)............................................................................................................................... 21
9-2. Write Disable (WRDI)................................................................................................................................ 22
9-3. Read Identification (RDID)........................................................................................................................ 23
9-4. Release from Deep Power-down (RDP), Read Electronic Signature (RES)............................................ 24
9-5. Read Electronic Manufacturer ID & Device ID (REMS)............................................................................ 26
9-6. QPI ID Read (QPIID)................................................................................................................................ 27
Table 6. ID Definitions ...............................................................................................................................27
9-7. Read Status Register (RDSR).................................................................................................................. 28
9-8. Write Status Register (WRSR).................................................................................................................. 32
Table 7. Protection Modes..........................................................................................................................33
9-9. Read Data Bytes (READ)......................................................................................................................... 35
9-10. Read Data Bytes at Higher Speed (FAST_READ)................................................................................... 36
9-11. Dual Read Mode (DREAD)....................................................................................................................... 38
9-12. 2 x I/O Read Mode (2READ).................................................................................................................... 39
9-13. Quad Read Mode (QREAD)..................................................................................................................... 40
9-14. 4 x I/O Read Mode (4READ).................................................................................................................... 41
9-15. Burst Read................................................................................................................................................ 44
9-16. Performance Enhance Mode.................................................................................................................... 45
9-17. Performance Enhance Mode Reset.......................................................................................................... 48
9-18. Sector Erase (SE)..................................................................................................................................... 49
9-19. Block Erase (BE32K)................................................................................................................................ 50
9-20. Block Erase (BE)...................................................................................................................................... 51
9-21. Chip Erase (CE)........................................................................................................................................ 52
9-22. Page Program (PP).................................................................................................................................. 53
9-23. 4 x I/O Page Program (4PP)..................................................................................................................... 55
9-24. Deep Power-down (DP)............................................................................................................................ 56
9-25. Enter Secured OTP (ENSO)..................................................................................................................... 57
P/N: PM2204
REV. 1.0, DEC. 31, 2014
2


Part Number MX25U6473F
Description FLASH MEMORY
Maker MACRONIX
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