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MOS-TECH

MT8103 Datasheet Preview

MT8103 Datasheet

P-Channel Enhancement Mode Field Effect Transistor

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MOS-TECH Semiconductor Co.,LTD
茂鈿半導體股份有限公司
MT8103
P-Channel Enhancement Mode Field Effect Transistor
Product Summary
VDS= -30V
ID= -13A (VGS= -10V)
≦ ΩRDS(ON) 10m @VGS= -10V
≦ ΩRDS(ON) 15.5m @VGS= -4.5V
Applications
▪ Notebook Computer
▪ Portable Battery Pack
Features
Advanced Trench Process Technology.
High Density Cell Design for Ultra Low
On-Resistance.
Lead free product is acquired.
RoHS Compliant.
Absolute Maximum Ratings (TA = 25 unless otherwise noted)
Symbol
VDS
VGS
ID
IDM
IS
PD
TJ, Tstg
Parameter
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current 1
Pulsed Drain Current 2
Continuous Source Current (Diode Conduction) 1
Maximum Power Dissipation 1
Operating Junction and Storage Temperature Range
10s Steady State
-30
±20
-13 -9
-50
-2.7 -1.36
3.0 1.5
-55 to 150
Units
V
V
A
A
A
W
Thermal Resistance Ratings
Symbol
Parameter
RthJA
Maximum Junction-to-Ambient 1
Notes:
1 Surface Mounted on 1” x 1” FR4 Board.
2 Pulse width limited by maximum junction temperature.
Rev2.0 Mar-28-2013
t 10 Sec
Steady State
Typical
33
70
Maximum
42
82
Unit
/W
www.mtsemi.com
Page 1 of 6




MOS-TECH

MT8103 Datasheet Preview

MT8103 Datasheet

P-Channel Enhancement Mode Field Effect Transistor

No Preview Available !

MOS-TECH Semiconductor Co.,LTD
茂鈿半導體股份有限公司
Electrical Characteristics (TA=25°C, unless otherwise noted)
Symbol
Parameter
Test Condition
Static Characteristics
BVDSS Drain-Source Breakdown Voltage
VGS = 0V, ID = -250µA
VGS(th) Gate Threshold Voltage
VGS = VDS, ID = -250µA
IGSS Gate-Body Leakage Current
VGS = ±20V, VDS = 0V
IDSS Zero Gate Voltage Drain Current
VDS = -24V, VGS = 0V
VDS = -24V, VGS = 0V, TJ = 70
RDS(on) Drain Source On State Resistance a
gfs Forward Transconductance a
VSD Diode Forward Voltage a
Dynamic Characteristics b
VGS = -10V, ID = -13A
VGS = -4.5V, ID = -10A
VDS = -15V, ID = -13A
IS = -2.7A, VGS = 0V
Ciss Input Capacitance
Coss Output Capacitance
VDS = -15V, VGS = 0V, f = 1MHz
Crss Reverse Transfer Capacitance
Qg Total Gate Charge
Qgs Gate-Source Charge
VDS = -15V, VGS = -5V, ID = -13A
Qgd Gate-Drain Charge
td(on)
Turn-On Delay Time
tr Rise Time
VDD = -15V, RL = 15Ω
Td(off)
Turn-Off Delay Time
ID = -1A, VGEN = -10V, RG = 6Ω
tf Fall Time
Rg Gate Resistance
VGS = 0, VDS = 0, f = 1MHz
trr Source-Drain Reverse Recovery Time IF = -2.1A, di/dt = 100A/µs
Note:
≦ ≦a. Pulse test; pulse width 300µs, duty cycle 2%.
b. Guaranteed by design, not subject to production testing.
MT8103
Min Typ Max Unit
-30 -
-V
-1.0 -1.5 -3.0
V
- - ±100 nA
- - -1
µA
- -10
- 8.5 10
mΩ
- 12.5 15.5
- 40 - S
- -0.74 -1.1 V
- 3340.0 -
- 577.0 -
pF
- 426.0 -
- 37.0 -
- 10.0 - nC
- 11.0 -
- 19.5 -
- 10.0 -
nSec
- 137.5 -
- 55.3 -
- 3.4 - Ω
- 60 100 nSec
Rev2.0 Mar-28-2013
www.mtsemi.com
Page 2 of 6


Part Number MT8103
Description P-Channel Enhancement Mode Field Effect Transistor
Maker MOS-TECH
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