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ME8107-G Datasheet Preview

ME8107-G Datasheet

P-Channel Enhancement Mode MOSFET

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ME8107/ME8107-G
P-Channel Enhancement Mode MOSFET, ESD Protected
GENERAL DESCRIPTION
The ME8107 is the P-Channel logic enhancement mode power field
effect transistors are produced using high cell density, DMOS trench
technology. This high density process is especially tailored to
minimize on-state resistance. These devices are particularly suited
for low voltage application such as cellular phone and notebook
computer power management and other battery powered circuits
where high-side switching and low in-line power loss are needed in a
very small outline surface mount package.
PIN CONFIGURATION
(SOP-8)
Top View
FEATURES
RDS(ON)7.2m@VGS=-10V
RDS(ON)12m@VGS=-4.5V
Super high density cell design for extremely low RDS(ON)
Exceptional on-resistance and maximum DC current
capability
APPLICATIONS
Power Management in Note book
Portable Equipment
Battery Powered System
DC/DC Converter
Load Switch
LCD Display inverter
e Ordering Information: ME8107(Pb-free)
ME8107-G (Green product-Halogen free)
Absolute Maximum Ratings (TA=25Unless Otherwise Noted)
Parameter
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current
Pulsed Drain Current
Maximum Power Dissipation*
Operating Junction Temperature
TA=25
TA=70
TA=25
TA=70
Thermal Resistance-Junction to Ambient*
Symbol
VDS
VGS
ID
IDM
PD
TJ
RθJA
Maximum Ratings
-35
±20
-13
-10
-52
2
1.3
-55 to 150
62.5
* The device mounted on 1in2 FR4 board with 2 oz copper
1.2
Mar, 2012-Ver1.3
Unit
V
V
A
A
W
℃/W
01




Matsuki

ME8107-G Datasheet Preview

ME8107-G Datasheet

P-Channel Enhancement Mode MOSFET

No Preview Available !

ME8107/ME8107-G
P-Channel Enhancement Mode MOSFET, ESD Protected
Electrical Characteristics (TA =25Unless Otherwise Specified)
Symbol
STATIC
VBR(DSS)
VGS(th)
IGSS
IDSS
Parameter
Drain-source breakdown voltage
Gate Threshold Voltage
Gate Leakage Current
Zero Gate Voltage Drain Current
RDS(ON)
Drain-Source On-State Resistancea
VSD Diode Forward Voltage
DYNAMIC
Qg Total Gate Charge
Qg Total Gate Charge
Qgs Gate-Source Charge
Qgd
td(on)
tr
td(off)
tf
Ciss
COSS
Crss
Gate-Drain Charge
Turn-On Delay Time
Turn-On Rise Time
Turn-Off Delay Time
Turn-Off Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Limit
ID=-10mA, VGS=0V
VGS= VDS, ID=-250μA
VDS=0V, VGS=±16V
VDS=-30V, VGS=0V
VGS=-10V, ID= -7A
VGS=-4.5V, ID= -6.5A
IDR=-7A, VGS=0V
VDD=-24V, VGS=-4.5V, ID=-13A
VDD=-24V, VGS=-10V, ID=-13A
VDD=-15V, RL =15Ω
VGS=-10V,RG=6Ω
VDS=-15V, VGS=0V, f=-1MHZ
Min Typ Max Unit
-35 V
-1 -3.0 V
±10 μA
-10 μA
5.5 7.2
mΩ
8 12
0.78 V
58
120
26
33
77
32
213
64
5330
710
242
nC
ns
pF
Notes: a. Pulse test: pulse width300us, duty cycle2%, Guaranteed by design, not subject to production testing.
b. Matsuki Electric/ Force mos reserves the right to improve product design, functions and reliability without notice.
1.2
Mar, 2012-Ver1.3
02


Part Number ME8107-G
Description P-Channel Enhancement Mode MOSFET
Maker Matsuki
Total Page 5 Pages
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