DS21552 - T1 Single-Chip Transceivers

Maxim Integrated

Datasheet Details

Complete DS1/ISDN.
PRI/J1 transceiver functionality.
Long and Short haul LIU.
Crystal.
less jitter attenuator.
Generates DSX.
1 and CSU line build-outs.
HDLC controller with 64-byte buffers Configurable for FDL or DS0 operation.
Dual two.
frame elastic store slip buffers that can connect to asynchronous backplanes up to 8.192MHz.
8.192MHz clock output locked to RCLK.
Interleaving PCM Bus Operation.
Per-channel loopback and.

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Published: Nov 5, 2017 |