DSSHA1 Description
The DSSHA1 coprocessor with 64-byte RAM is a synthesizable register transfer level (RTL) implementation of the FIPS 180-3 Secure Hash Algorithm (SHA-1), eliminating the need to develop software to perform the plex SHA-1 putation required for authenticating SHA-1 devices. The device can output the 20-byte MAC result from registers required for parison against SHA-1 slave devices. When incorporated into a design,...
DSSHA1 Key Features
- SHA-1 putations Within 670 Clock Cycles (13.4µs at a Typical Frequency of 50MHz)
- Area Estimate is 102,256µm2 in TSMC CL018G (0.18µm Generic Process)
- Dedicated Hardware-Accelerated SHA-1 Engine for Generating MACs
- 64-Byte RAM for Message Input
- Five 32-Bit Registers to Read MAC Result
- Available in Synthesizable Verilog®
- Made as a Low-Level Module to be Instantiated by
- Includes Test Bench