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Maxim Integrated Semiconductor Electronic Components Datasheet

DS31404 Datasheet

Dual DPLL Timing IC

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ABRIDGED DATA SHEET
19-5710; Rev 0; 12/10
DS31404
4-Input, 8-Output, Dual DPLL Timing IC
with Sub-ps Output Jitter
General Description
Features
The DS31404 is a flexible, high-performance timing IC
for diverse frequency conversion and frequency
synthesis applications. On each of its four input clocks
and eight output clocks, the device can accept or
generate nearly any frequency between 2kHz and
750MHz. The device offers two independent DPLLs to
serve two independent clock-generation paths.
The input clocks are divided down, fractionally scaled as
needed, and continuously monitored for activity and
frequency accuracy. The best input clock is selected,
manually or automatically, as the reference clock for
each of the two flexible, high-performance digital PLLs.
Each DPLL lock to the selected reference and provides
programmable bandwidth, very high resolution holdover
capability, and truly hitless switching between input
clocks. The digital PLLs are followed by a clock
synthesis subsystem that has four fully programmable
digital frequency synthesis blocks, two high-speed low-
jitter APLLs, and eight output clocks, each with its own
32-bit divider and phase adjustment. The APLLs provide
fractional scaling and output jitter less than 1ps RMS.
For telecom systems, the DS31404 has all required
features and functions to serve as a central timing
function or as a line card timing IC. With a suitable
oscillator the DS31404 meets the requirements of
Stratum 2, 3E, 3, 4E, and 4, G.812 Types I–IV, G.813,
and G.8262.
Applications
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Frequency Conversion Applications in a Wide Variety of
Equipment Types
Telecom Line Cards or Timing Cards with Any Mix of
SONET/SDH, Synchronous Ethernet and/or OTN
Ports in WAN Equipment Including MSPPs, Ethernet
Switches, Routers, DSLAMs, and Base Stations
Ordering Information
PART
DS31404GN+
TEMP RANGE
-40C to +85C
PIN-PACKAGE
256 CSBGA
+Denotes a lead(Pb)-free/RoHS-compliant package.
SPI is a trademark of Motorola, Inc.
Four Input Clocks
Differential or CMOS/TTL Format
Any Frequency from 2kHz to 750MHz
Fractional Scaling for 64B/66B and FEC
Scaling (e.g., 64/66, 237/255, 238/255) or Any
Other Downscaling Requirement
Continuous Input Clock Quality Monitoring
Automatic or Manual Clock Selection
Three 2/4/8kHz Frame Sync Inputs
Two High-Performance DPLLs
Hitless Reference Switching on Loss of Input
Automatic or Manual Phase Build-Out
Holdover on Loss of All Inputs
Programmable Bandwidth, 0.5mHz to 400Hz
Four Digital Frequency Synthesizers
Each Can Slave to Either DPLL
Produce Any 2kHz Multiple Up to 77.76MHz
Per-DFS Clock Phase Adjust
Two Output APLLs
Output Frequencies to 750MHz
High Resolution Fractional Scaling for FEC
and 64B/66B (e.g., 255/237, 255/238, 66/64)
or Any Other Scaling Requirement
Less than 1ps RMS Output Jitter
Simultaneously Produce Two Low-Jitter Rates
from the Same Reference (e.g., 622.08MHz
for SONET and 156.25MHz for 10GE)
Eight Output Clocks in Four Groups
Nearly Any Frequency from < 1Hz to 750MHz
Each Group Slaves to a DFS Clock, Any APLL
Clock, or Any Input Clock (Divided and Scaled)
Each Has a Differential Output (2 CML, 2
LVDS/LVPECL) and Separate CMOS/TTL Output
32-Bit Frequency Divider Per Output
Two Sync Pulse Outputs: 8kHz and 2kHz
General Features
Suitable Line Card IC or Timing Card IC for
Stratum 2/3E/3/4E/4, SMC, SEC/EEC, or SSU
Accepts and Produces Nearly Any Frequency
Up to 750MHz Including 1Hz, 2kHz, 8kHz,
NxDS1, NxE1, DS2/J2, DS3, E3, 2.5M, 25M,
125M, 156.25M, and Nx19.44M Up to 622.08M
Internal Compensation for Local Oscillator
Frequency Error
SPI™ Processor Interface
1.8V Operation with 3.3V I/O (5V Tolerant)
Maxim Integrated Products 1
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple
revisions of any device may be simultaneously available through various sales channels. For information about device
errata, go to: www.maxim-ic.com/errata. For pricing, delivery, and ordering information, please contact Maxim Direct at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.


Maxim Integrated Semiconductor Electronic Components Datasheet

DS31404 Datasheet

Dual DPLL Timing IC

No Preview Available !

ABRIDGED DATA SHEET
Application Example
DS31404
19.44MHz, 38.88MHz,
25MHz, etc.
clock monitoring and selection,
hitless switching, holdover, frequency
conversion, fractional scaling,
jitter attenuation
system timing
from master and slave
timing cards
DS31404
IC1
IC2 DPLL1 Path
n OC1, OC2
line timing
to master and slave
timing cards
OC4
OC5
DPLL2 Path
n IC3, IC4
clocks to line card SERDES
SONET/SDH, 1GE, 10GE, OTN, FC, etc.
3 unrelated frequencies simultaneously at <1ps rms jitter
plus other frequencies at somewhat higher jitter
recovered line clocks from SERDES
SONET/SDH, 1GE, 10GE, OTN, FC etc.
frequencies can be unrelated to one another
8kHz, 19.44MHz,
38.88MHz, 25MHz, etc.
clock monitoring and selection,
undo fractional scaling,
frequency conversion
155.52M, 622.08M, 25M,
125M, 156.25M, etc. with or
without fractional scaling for
FEC, 64B/66B, etc.
MANY other rates possible,
including DS1, E1, DS3, E3,
10M and Nx19.44M.
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2 of 5


Part Number DS31404
Description Dual DPLL Timing IC
Maker Maxim Integrated Products
PDF Download

DS31404 Datasheet PDF






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