o 80Msps Minimum Sampling Rate o -82dBFS Noise Floor o Excellent Dynamic Performance 80dB/79.2dB SNR at fIN = 10MHz/70MHz and -2dBFS 96dBc/102dBc Single-Tone SFDR1/ SFDR2 at fIN = 10MHz 84.3dBc/100dBc Single-Tone SFDR1/ SFDR2 at fIN = 70MHz o Less than 0.1ps Sampling Jitter o 1.1W Power Dissipation o 2.56VP-P Fully Differential Analog Input Voltage Range o CMOS-Compatible Two’s-Complement Data Output o Separate Data Valid Clock and Over-Range Outputs o Flexible Input Clock Buffer o 3.3V Analog P.
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MAX19586. For precise diagrams, and layout, please refer to the original PDF.
19-3758; Rev 0; 8/05 KIT ATION EVALU E L B AVAILA High-Dynamic-Range, 16-Bit, 80Msps ADC with -82dBFS Noise Floor General Description Features o 80Msps Minimum Sampling R...
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S Noise Floor General Description Features o 80Msps Minimum Sampling Rate o -82dBFS Noise Floor o Excellent Dynamic Performance 80dB/79.2dB SNR at fIN = 10MHz/70MHz and -2dBFS 96dBc/102dBc Single-Tone SFDR1/ SFDR2 at fIN = 10MHz 84.3dBc/100dBc Single-Tone SFDR1/ SFDR2 at fIN = 70MHz o Less than 0.1ps Sampling Jitter o 1.1W Power Dissipation o 2.56VP-P Fully Differential Analog Input Voltage Range o CMOS-Compatible Two’s-Complement Data Output o Separate Data Valid Clock and Over-Range Outputs o Flexible Input Clock Buffer o 3.3V Analog Power Supply; 1.8V Digital Output Supply o Small 8mm x 8mm x 0.8mm 56-Pin Thin QFN Packa
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MAX19586 Datasheet
