MAX9254 Description
The MAX9242/MAX9244/MAX9246/MAX9254 deserialize three LVDS serial-data inputs into 21 single-ended LVCMOS/ LVTTL outputs. A separate parallel-rate LVDS clock provides the timing for deserialization. The MAX9242/ MAX9244/MAX9246/MAX9254.
MAX9254 Key Features
- Programmable ±4%, ±2%, or OFF Spread-Spectrum Output for Reduced EMI
- Programmable DC-Balanced or Non-DC-Balanced Modes
- DC Balance Allows AC-Coupling for Wider Input mon-Mode Voltage Range
- Spread Spectrum Operates in DC-Balanced or Non-DC-Balanced Mode
- High Output Drive (MAX9254)
- π / 4 Deskew by Oversampling (MAX9242/MAX9244/MAX9254)
- 16MHz-to-34MHz (DC-Balanced) and 20MHz-to40MHz (Non-DC-Balanced) Operation (MAX9242/MAX9244/MAX9254)
- 6MHz-to-18MHz (DC-Balanced) and 8MHz-to-20MHz (Non-DC-Balanced) Operation (MAX9246)
- Rising-Edge (MAX9242) or Falling-Edge (MAX9244/MAX9246/MAX9254) Output Strobe
- High-Impedance Outputs when PWRDWN is Low Allow Output Busing