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DSC557-03 Datasheet Preview

DSC557-03 Datasheet

Crystal-less Two Output PCIe Gen1/2/3 Clock Generator

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DSC557-03
Crystal-less Two Output PCIe Gen1/2/3 Clock Generator
General Description
Features
The DSC557-03 is a crystal-less, two output
PCI express clock generator meeting Gen1,
Gen2, and Gen3 specifications. The clock
generator uses proven silicon MEMS
technology to provide 100MHz* differential
output clocks with excellent jitter and
stability over a wide range of supply
voltages and temperatures. By eliminating
the external quartz crystal, the DSSC557-03
significantly enhances reliability and
accelerates product development, while
meeting stringent clock performance criteria
for a variety of communications, storage,
and networking applications.
DSC557-03 has an Output Enable / Disable
feature allowing it to disable the outputs
when OE is low. The device is available in
two different packages; a “drop-in”
replacement 16 pin TSSOP or a space
saving 14 pin QFN (77% less board space).
Additional output formats are also available
in any combination of LVPECL, LVDS, and
HCSL.
Block Diagram
Meets PCIe Gen1, Gen2 & Gen3 specs.
Available Output Formats:
o HCSL, LVPECL, or LVDS
o HCSL/LVPECL, HCSL/LVDS, LVPECL/LVDS
Wide Temperature Range
o Ext. Industrial: -40° to 105° C
o Industrial: -40° to 85° C
o Ext. commercial: -20° to 70° C
Supply Range of 2.25 to 3.6 V
Low Power Consumption
o 30% lower than competing devices
Excellent Shock & Vibration Immunity
o Qualified to MIL-STD-883
Available Footprints:
o 16 TSSOP
o 14 QFN
Lead Free & RoHS Compliant
Short Lead Time: 2 Weeks
Applications
Control Circuitry
MEMS
PLL
OE
Output
Control
and
Divider
CLK0+
CLK0-
CLK1-
CLK1+
* Clk0+/- and Clk1+/- are 100 MHz as per PCIe
standards. For other frequencies, please
contact the factory.
Communications/Networking
o Ethernet
o 1G, 10GBASE-T/KR/LR/SR, and FcoE
o Routers and Switches
o Gateways, VoIP, Wireless AP’s
o Passive Optical Networks
Storage
o SAN, NAS, SSD, JBOD
Embedded Applications
o Industrial, Medical, and Avionics
o Security Systems and Office
Automation
o Digital Sinage, POS and others
Consumer Electronics
o Smart TV, Bluray, STB
_____________________________________________________________________________________________________________________________ _________________
DSC557-03
Page 1
MK-QB-P-D-120917-01-2




Micrel

DSC557-03 Datasheet Preview

DSC557-03 Datasheet

Crystal-less Two Output PCIe Gen1/2/3 Clock Generator

No Preview Available !

DSC557-03
Crystal-less Two Output PCIe Gen1/2/3 Clock Generator
Specifications (Unless specified otherwise: T=25° C, VDD =3.3V)
Parameter
Supply Voltage1
Supply Current
Supply Current2
(Two HCSL Outputs)
Frequency Stability
Startup Time3
Input Logic Levels
Input logic high
Input logic low
Output Disable Time4
Output Enable Time
Pull-Up Resistor2
Condition
Min.
Typ.
Max. Unit
VDD
2.25
IDD
EN pin low outputs are
disabled
EN pin high outputs are
IDD
enabled
RL=50 Ω, FO1=FO2=100 MHz
Includes frequency variations
Δf
due to initial tolerance, temp.
and power supply voltage
tSU
3.6
V
21
23
mA
60
mA
±100
±50
5
ppm
ms
VIH
0.75xVDD
-
V
VIL
-
0.25xVDD
tDA
5
ns
tEN
20
ns
Pull-up on OE pin
40
kΩ
Parameter
Output Logic Levels
Output logic high
Output logic low
Pk to Pk Output Swing
Output Transition time4
Rise Time
Fall Time
Frequency
Output Duty Cycle
Period Jitter5
VOH
VOL
tR
tF
f0
SYM
JPER
RJ
HCSL Outputs6
Condition
RL=50Ω
Single-Ended
20% to 80%
RL=50Ω, CL= 2pF
Single Frequency
Differential
FO1=FO2=100 MHz
PCIe Gen 1.1
TJ=DJ + 14.069 x RJ (BER 10-12)
Min.
0.725
-
200
2.3
48
Typ.
750
1007
2.5
0.540
Max.
-
0.1
400
460
52
Unit
V
mV
ps
MHz
%
psRMS
PsRMS
Jitter, Phase
(Common Clock
Architecture)
Integrated Phase Noise
(Data Clock
Architecture)
DJ
TJ
JRMS-CCHF
JRMS-CCLF
JRMS-CC
JRMS-DCHF
JRMS-DCLF
JRMS-DC
PCIe Gen 1.1
TJ=DJ + 14.069 x RJ (BER 10-12)
PCIe Gen 2.1, 1.5 MHz to
Nyquist
PCIe Gen 2.1, 10 kHz to 1.5 MHz
PCIe Gen 3.0
PCIe Gen 2.1, 1.5 MHz to
Nyquist
PCIe Gen 2.1, 10 kHz to 1.5 MHz
PCIe Gen 3.0
0.832
8.536
0.458
0.030
0.165
0.561
1.778
0.147
41.98
86.08
3.18
3.08
1.08
4.08
7.58
1.08
psp-p
psRMS
psRMS
psRMS
psRMS
psRMS
psRMS
Notes:
1. VDD should be filtered with 0.01uf capacitor.
2. Output is enabled if OE pin is floated or not connected.
3. tsu is time to 100PPM stable output frequency after VDD is applied and outputs are enabled.
4. Output Waveform and Connection Diagram define the parameters.
5. Period Jitter includes crosstalk from adjacent output.
6. Contact Sales@Discera.com for alternate output options (LVPECL, LVDS, LVCMOS).
7. Contact Sales@Discera.com for alternative frequency options
8. Jitter limits established by Gen 1.1, Gen 2.1, and Gen 3.0 PCIe standards.
_____________________________________________________________________________________________________________________________ _________________
DSC557-03
Page 2
MK-QB-P-D-120917-01-2



Part Number DSC557-03
Description Crystal-less Two Output PCIe Gen1/2/3 Clock Generator
Maker Micrel
Total Page 3 Pages
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DSC557-03 Datasheet PDF





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