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PL502-38 Datasheet Preview

PL502-38 Datasheet

750kHz - 800MHz Low Phase Noise Multiplier VCXO

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PL502-35/-37/-38/-39
750kHz 800MHz Low Phase Noise Multiplier VCXO
Universal Low Phase Noise ICs
FEATURES
PIN CONFIGURATION
Selectable 750kHz to 800MHz range
Low phase noise output (@ 10kHz frequency off-
set, -142dBc/Hz for 19.44MHz, -125dBc/Hz for
155.52MHz, -115dBc/Hz for 622.08MHz)
LVCMOS (PL502-37), LVPECL (PL502-35 and
PL502-38) or LVDS (PL502-39) output
12MHz to 25MHz crystal input
No external load capacitor or varicap required.
Output Enable selector
Wide pull range (±200 ppm)
Selectable /16 to x32 frequency divider/multiplier
3.3V operation
Available in 16-Pin TSSOP or 16-pin 3x3mm QFN
GREEN/RoHS compliant packages
(Top View)
VDD
XIN
XOUT
SEL3^
SEL2^
OE
VCON
GND
1
2
3
4
5
6
7
8
1
6
SEL0^
1
5
SEL1^
1
4
GND
1
3
CLKC
1
2
VDD
1
1
CLKT
1
0
GND
9 GND
TSSOP-16L
^: Internal pull-up
*: On 3x3 package, PL502-35/-38 do not have SEL0 available: Pin 10
is VDD, pin 11 is GND. However, PL502-37/-39 have SEL0 (pin 10),
and pin11 is VDD. See pin assignment table for details.
DESCRIPTION
The PL502-35 (LVPECL with inverted OE), PL502-37
(LVCMOS), PL502-38 (LVPECL), and PL502-39
(LVDS) are high performance and low phase noise
VCXO IC chips. They provide phase noise perfor-
mance as low as 125dBc at 10kHz offset (at
155MHz), by multiplying the input crystal frequency up
to 32x. The wide pull range (±200 ppm) and very low
jitter make them ideal for a wide range of applications,
including SONET/SDH and FEC. They accept funda-
mental parallel resonant mode crystals from 12MHz to
25MHz.
BLOCK DIAGRAM
SEL[3:0]
VCON
XIN
XOUT
Oscillator
Amplifier
w/
integrated
varicaps
PLL
(Phase
Locked
Loop)
PLL by-pass
OE
CLKC
CLKT
PL502-3x
XOUT
SEL3^
SEL2^
OE
12
13
11 10
9
8
14 PL502-3x 7
15 6
16 5
123 4
GND
CLKC
VDD
CLKT
QFN-16L
OUTPUT ENABLE LOGICAL LEVELS
Part #
OE
State
PL502-38
PL502-35
PL502-37
PL502-39
0 (Default)
1
0
1 (Default)
Output enabled
Tri-state
Tri-state
Output enabled
OE input: Logical states defined by LVPECL levels for PL502-38
Logical states defined by LVCMOS levels for PL502-37/-39
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 4/15/13 Page 1




Micrel

PL502-38 Datasheet Preview

PL502-38 Datasheet

750kHz - 800MHz Low Phase Noise Multiplier VCXO

No Preview Available !

PL502-35/-37/-38/-39
750kHz 800MHz Low Phase Noise Multiplier VCXO
Universal Low Phase Noise ICs
FREQUENCY SELECTION TABLE
SEL3
SEL2
SEL1
SEL0
Selected Multiplier
0011
0110
0111
1001
1010
1011
1100
1101
1110
1111
Note: SEL0 is not available (always “1”) for PL502-35 and PL502-38 in 3x3mm package
Fin x 32
Fin / 8
Fin x 2
Fin / 2
Fin / 16
Fin x 4
Fin / 4
Fin x 8
Fin x 16
No multiplication
PIN DESCRIPTIONS PL502-35 and PL502-38 (see next page for PL502-37/-39)
Name
TSSOP
Pin number
3x3mm QFN
Pin number
Type
Description
XIN 2 12 I Crystal input (See Crystal Specification on page 4)
XOUT
3
13 I Crystal output (See Crystal Specification on page 4)
OE 6 16 I Output enable pin (See OE logic state table on page 1)
VCON
7
1 I Voltage Control input
GND
8,9,10,14
2,3,4,8,11
P Ground connection
CLKT
11
5 O LVPECL True output
CLKC
13
7 O LVPECL Complementary output
SEL0
SEL1
SEL2
SEL3
16 Not available I
15
9
I
Multiplier selector pins. These pins have an internal pull-
up that will default SEL to ‘1’ when not connected to
5 15 I GND.
4 14 I
VDD 1, 12 6,10 P +3.3V power supply.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 4/15/13 Page 2


Part Number PL502-38
Description 750kHz - 800MHz Low Phase Noise Multiplier VCXO
Maker Micrel
Total Page 10 Pages
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