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Micrel Semiconductor

MDB1900ZC Datasheet Preview

MDB1900ZC Datasheet

Zero Delay Buffer

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MDB1900ZC
Zero Delay Buffer
for PCIe (Gen1/Gen2/Gen3),
SAS, SATA, ESI, and QPI
General Description
The MDB1900ZC is a true zero delay buffer with a fully
integrated, high-performance, low-power, and low-phase
noise programmable PLL.
The MDB1900ZC is capable of distributing the reference
clocks for PCIe (Gen1/Gen2/Gen3), SATA, ESI, SAS, SMI,
and Intel® Quickpath Interconnect (QPI). The MDB1900ZC
works in conjunction with a CK410B+, CK509B, or
CK420BQ clock synthesizer to provide reference clocks to
multiple agents.
The MDB1900ZC is designed for Intel’s DB1900Z
specification with the exception that the zero delay buffer
feedback path is inside the IC and does not need to be
built onto the PCB.
Datasheets and support documentation are available on
Micrel’s website at: www.micrel.com.
Block Diagram
Features
Supports zero delay (0ps) buffer mode for 100MHz and
133MHz clock frequencies.
Internal feedback path for zero delay (PLL) mode
Zero delay (PLL) mode can filter jitter in incoming clock
Selectable PLL bandwidth for PLL mode
Supports fanout buffer mode for clock frequencies
between 0MHz and 250MHz
Differential input reference with HCSL logic (0V~0.7V)
Nineteen differential HCSL-compatible clock output
pairs
Eight dedicated OE# pins to control their assigned
output. Glitch free assertion/de-assertion.
Spread spectrum modulation tolerant for EMI reduction
SMBus interface for controlling output properties
(enable/disable and delay tuning)
Disabled outputs in power-down mode for maximum
power savings
Nine selectable SMBus addresses so multiple devices
can share the same SMBus
3.3V or 2.5V operation
Commercial or industrial temperature ranges
72-pin 10mm × 10mm QFN package
GREEN, RoHS, and PFOS compliant
Applications
PCI Express timing (Gen1/2/3) in Intel platforms,
specifically the Romley platform
SATA/SAS timing (storage)
ESI and SMI systems (storage)
Intel Quickpath Interconnect
Key Specifications
Cycle-to-cycle jitter (PLL mode): <35ps
Output-to-output skew: <35ps
Input-to-output delay (PLL mode): Fixed at 0ps
Input-to-output delay variation (PLL mode): 13ps
Phase jitter, PCIe Gen3: 0.25ps
Accumulated jitter, QPI 9.6Gbps: <0.15ps
Intel is a registered trademark of Intel Corporation.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
September 3, 2015
Revision 1.2
tcghelp@micrel.com or (408) 955-1690




Micrel Semiconductor

MDB1900ZC Datasheet Preview

MDB1900ZC Datasheet

Zero Delay Buffer

No Preview Available !

Micrel, Inc.
Ordering Information
Part Number
Marking
Shipping
Ambient Temperature Range
MDB1900ZCQY TR MDB1900ZCQ Tape and Reel
–40°C to +85°C
MDB1900ZCQZ TR MDB1900ZCQ Tape and Reel
0°C to +70°C
Note:
1. Device is GREEN, RoHS, and PFOS compliant. Lead finish is 100% matte tin.
Pin Configuration
MDB1900ZC
Package(1)
72-Pin 10mm × 10mm QFN
72-Pin 10mm × 10mm QFN
72-Pin 10mm × 10mm QFN
September 3, 2015
2 Revision 1.2
tcghelp@micrel.com or (408) 955-1690


Part Number MDB1900ZC
Description Zero Delay Buffer
Maker Micrel Semiconductor
Total Page 30 Pages
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