Six Decade Counter, Latch
The six decade counter is synchronously incremented or
decremented on the positive edge of the count input signal.
A Schmitt trigger on this input provides hysteresis for protec-
tion against both a noisy environment and double triggering
due to a slow rising edge at the count input.
The count inhibit can be changed in coincidence with
the positive transition of the count input; the count input is
inhibited when the count inhibit is high.
The counter will increment when up/down input is high (VSS)
and will decrement when up/down input is low. The up/down
input can be changed 0.75 µs prior to the positive transition
of the count input.
The clear input is asynchronous and will reset all decades to
zero when brought high but does not affect the six digit latch
or the scan counter.
As long as store input is low, data is continuously transferred
from the counter to the display. Data in the counter will be
latched and displayed when store input is high. Store can be
changed in coincidence with the positive transition of the
The counter is loaded digit by digit corresponding to the digit
strobe outputs. BCD thumb wheel switches with four diodes
per decade connected between the digit strobe outputs and
the BCD inputs is one method to supply BCD data for
loading the counter decades.
The load counter pulse must be at VSS 2 µs prior to the
positive transition of the digit strobe of the digit to be loaded.
The load counter pulse may be removed after the positive
transition of the digit strobe since the chip internally latches
this signal. The BCD data to be loaded must be valid through
the negative transition of the digit strobe.
The seven segment outputs are open drain capable of
sourcing 10mA average current per segment over one digit
cycle. Segments are on when at VSS. The Carry, Equal,
Zero, BCD and digit strobe outputs are push pull and are on
when at VSS. All inputs except Counter BCD, Register BCD,
and SCAN inputs are high impedance CMOS compatible.
Three basic outputs originate from the counter: zero output,
equal output, and carry output. Each output goes high on the
positive (VSS) going edge of the count input under the
Zero output goes high for one count period when all decades
contain zero. During a load counter operation the zero
output is inhibited.
Equal output goes high for one count period when the con-
tents of the counter and compare register are equal. The
equal output is inhibited by a load counter or load register
operation, which lasts until the next interdigit blanking period
following a negative transition of Load Counter or Load
The carry output goes high with the leading edge of the
count input at the count of 000000 when counting up or at
999999* when counting down and goes low with the negative
going edge of the same count input.
A count frequency of 1 MHz can be achieved if the equal
output, zero output and carry output are not used. These
outputs do not respond at this frequency due to their output
delay illustrated on the timing diagram.
Six Decade Compare Register
The register is loaded identically to the load counter paragraph
described previously. The register may be loaded
independently of the counter, however, the clear input will
not remove the register contents. Contents of the register
are not displayed by the BCD or seven segment outputs.
BCD Seven Segment Outputs
BCD or seven segment outputs are available. Digit strobes
are decoded internally by a divide by six Johnson counter.
This counter scans from MSD to LSD. By bringing the SET
input low, this counter will be forced to the MSD decade
count. During this time the segment outputs are blanked to
protect against display burn out.
BCD outputs are valid for MSD when SET is low. Applying
VSS to SET allows normal scan to resume. Digit 6 output is
active (VSS) until the next scan clock pulse brings up digit 5
The segment outputs and digit strobes are blanked during
the interdigit blanking time. Leading zero blanking affects
only the segment outputs. This option is disabled by bringing
the LZB input high. Typically the interdigit blanking time is 5
to 25 µs when using the internal scan oscillator.
BCD output data changes at the beginning of the interdigit
blanking time. Therefore the BCD output data is valid when
the positive transition of a digit output occurs.
The MIC50395 has an internal scan oscillator. The frequency
of the scan oscillator is determined by an external capacitor
between VSS or VDD and scan input. The wave form present
on the scan oscillator input is triangular in the self oscillate
An external oscillator may also be used to drive the scan
input. In either case, external capacitors of 150pF each will
be required from VSS to Counter BCD inputs and register
BCD inputs. This will allow asynchronous loading of the
In the internal drive mode the interdigit blanking time will be
the sum of the negative dwell period of the external oscillator
and the normal self oscillate blanking time. (5→25 µs). Dis-
play brightness can be controlled by the duty cycle of the
external scan oscillator.
*Carry occurs at 99:59:59 for the 50396 and 59:59:99 for the 50397