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Micrel Semiconductor

PL123S-09 Datasheet Preview

PL123S-09 Datasheet

Spread-Compatible Low Skew Zero Delay Buffer

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PL123S-05/-09
Spread-Compatible Low Skew Zero Delay Buffer
FE AT UR E S
DESCRIPTION
Frequency Range 10MHz to 134 MHz
Output Options:
o 5 outputs PL123S-05
o 9 outputs PL123S-09
Zero input - output delay
Optional Drive Strength:
Standard (8mA) PL123S-05/-09
High (12mA) PL123S-05H/-09H
3.3V, ±10% operation
Available in Commercial and Industrial temperature
ranges
Available in 16-Pin SOP or TSSOP (PL123S-09),
and 8-Pin SOP (PL123S-05) packages
Spread-compatible with spread-spectrum modula-
tion clock inputs
The PL123S-05/-09 (-05H/-09H for High Drive) are high
performance, low skew, low jitter zero delay buffers
designed to distribute high speed clocks. They have
one (PL123S-05) or two (PL123S-09) low-skew output
banks, of 4 outputs each, that are synchronized with
the input. The PL123S-09 allows control of the banks
of outputs by using the S1 and S2 inputs as shown in
the Selector Definition table on page 2.
The synchronization is established via CLKOUT feed
back to the input of the PLL. Since the skew between
the input and output is less than 100ps, the device
acts as a zero delay buffer. The input output propaga-
tion delay can be advanced or delayed by adjusting the
load on the CLKOUT pin.
These parts are not intended for 5V input-tolerant ap-
plications.
BLOCK DIAGRAM
REF PLL
Mux
S1 Selector
Inputs
S2 (PL123S-09 Only)
CLKOUT
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
REF
CLKA2
CLKA1
GND
1
2
3
4
REF
CLKA1
CLKA2
VDD
GND
CLKB1
CLKB2
S2
1
2
3
4
5
6
7
8
8 CLKOUT
7 CLKA4
6 VDD
5 CLKA3
16 CLKOUT
15 CLKA4
14 CLKA3
13 VDD
12 GND
11 CLKB4
10 CLKB3
9 S1
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 12/14/11 Page 1




Micrel Semiconductor

PL123S-09 Datasheet Preview

PL123S-09 Datasheet

Spread-Compatible Low Skew Zero Delay Buffer

No Preview Available !

PL123S-05/-09
PIN DESCRIPTIONS
Spread-Compatible Low Skew Zero Delay Buffer
Name
PL123S-09
TSSOP-16L, SOP-16L
PL123S-05
SOP-8L
Type
Description
REF[1]
1 1 I Input reference frequency
CLKA1[2]
2
3 O Buffered clock output, Bank A
CLKA2[2]
3
2 O Buffered clock output, Bank A
VDD 4,13 6 P VDD connection
GND 5,12 4 P GND connection
CLKB1[2]
6
- O Buffered clock output, Bank B
CLKB2[2]
7
- O Buffered clock output, Bank B
S2[3] 8 - I Selector input
S1[3] 9 - I Selector input
CLKB3[2]
10
- O Buffered clock output, Bank B
CLKB4[2]
11
- O Buffered clock output, Bank B
CLKA3[2]
14
5 O Buffered clock output, Bank A
CLKA4[2]
CLKOUT [2 ]
15
16
7 O Buffered clock output, Bank A
8
O
Buffered clock output. Internal feedback
on this pin.
Notes: 1: Weak pull-down. 2: Weak pull-down on all outputs. 3: Weak Pull-Up on S1 and S2
SELECTOR DEFINITION FOR PL123S-09
S2
S1
CLOCK A1A4 CLOCK B1B4
(Bank A)
(Bank B)
0 0 Three-state Three-state
01
Driven
Three-state
10
11
Driven
Driven
Driven
Driven
CLKOUT
Driven
Driven
Driven
Driven
Output Source
PLL
PLL
Reference
PLL
PLL Shutdown
N
N
Y
N
INPUT / OUTPUT SKEW CONTROL
The PL123S-05/-09 will achieve Zero Delay from input to output when all the outputs are loaded equally . Adjust-
ments to the input/output delay can be made by adding additional loading to the CLKOUT pin.
Please contact Micrel for more information.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 12/14/11 Page 2


Part Number PL123S-09
Description Spread-Compatible Low Skew Zero Delay Buffer
Maker Micrel Semiconductor
Total Page 9 Pages
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