Download SY10-100EP451L Datasheet PDF
SY10-100EP451L datasheet preview
SY10-100EP451L page 2
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SY10-100EP451L Key Features

  • 450ps typical propagation delay
  • Maximum frequency > 3.0GHz typical
  • Asynchronous Master Reset
  • 20ps skew within device, 35ps skew device-to-device
  • PECL mode operating range
  • VCC = 3.0V to 3.6V with VEE = 0V
  • NECL mode operating range
  • VCC = 0V with VEE = -3.0V to -3.6V
  • Open input default state
  • Safety clamp on inputs

Related Micrel Semiconductor Datasheets

Part Number Description
SY100E016 8-BIT SYNCHRONOUS BINARY UP COUNTER
SY100E101 QUAD 4-INPUT OR/NOR GATE
SY100E104 QUINT 2-INPUT AND/NAND GATE
SY100E107 QUINT 2-INPUT XOR/XNOR GATE
SY100E111 1:9 DIFFERENTIAL CLOCK DRIVER

SY10-100EP451L Description

The SY10/100EP451L is a 6-bit fully differential register with mon clock and single-ended Master Reset (MR). It is ideal for very high frequency applications where a registered data path is necessary. All inputs have an internal 75kΩ pull-down resistor.