SY100H842 enable equivalent, single supply quad pecl-to-ttl output enable.
s Translates positive ECL-to-TTL (PECL-to-TTL) s 300ps pin-to-pin skew s 500ps part-to-part skew s Differential internal design for increased noise
immunity and stable th.
The SY10/100H842 are single supply, low skew translating 1:4 clock drivers.
The devices feature a 24mA TTL output stage, with AC performance specified into a 50pF load capacitance. A HIGH on the enable pin (EN) forces all outputs LOW.
As frequencies .
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