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SY10EP451L Key Features

  • 450ps typical propagation delay Maximum frequency > 3.0GHz typical Asynchronous Master Reset 20ps skew within device, 35
  • VCC = 3.0V to 3.6V with VEE = 0V NECL mode operating range
  • VCC = 0V with VEE = -3.0V to -3.6V Open input default state Safety clamp on inputs Available in 32-pin TQFP

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SY10EP451L Description

The SY10/100EP451L is a 6-bit fully differential register with mon clock and single-ended Master Reset (MR). It is ideal for very high frequency applications where a registered data path is necessary. All inputs have an internal 75k Ω pull-down resistor.