General Description
The Microchip Technology Inc. 48L256 serial EERAM
has an SRAM memory core with hidden EEPROM
backup. The device can be treated by the user as a full
symmetrical read/write SRAM. Backup to EEPROM is
handled by the device on any power disrupt, so the
user can effectively view this device as an SRAM that
never loses its data.
The device is structured as a 256-Kbit SRAM with
EEPROM backup in each memory cell. The SRAM is
organized as 32,768 x 8 bits and uses the SPI serial
interface. The SPI bus uses three signal lines for
communication: clock input (SCK), data in (SI), and
data out (SO). Access to the device is controlled
through a Chip Select (CS) input, allowing any number
of devices to share the same bus.
The SRAM is a conventional serial SRAM: it allows
symmetrical reads and writes and has no limits on cell
usage. The backup EEPROM is invisible to the user
and cannot be accessed by the user independently.
The device includes circuitry that detects VCC
dropping below a certain threshold, shuts its
connection to the outside environment, and transfers
all SRAM data to the EEPROM portion of each cell for
safe keeping. When VCC returns, the circuitry
automatically returns the data to the SRAM and the
user’s interaction with the SRAM can continue with the
same data set.
Block Diagram
VCC
VCAP
Power
Control
Block
CS
SO
SI
SCK
HOLD
SPI Control Logic
and Address
Decoder
STATUS
Register
Memory Address
and Data Control
Logic
SRAM
32K x 8
EEPROM
32K x 8
STORE
RECALL
48L256
Powering the Device During SRAM to
EEPROM Backup (VCAP)
A small capacitor (typically 33 μF) is required for the
proper operation of the device. This capacitor is placed
between VCAP (pin 3) and the system VSS (see Normal
Device Operation). When power is first applied to the
device, this capacitor is charged to VCC through the
device (see Normal Device Operation). During normal
SRAM operation, the capacitor remains charged to
VCC and the level of system VCC is monitored by the
device. If system VCC drops below a set threshold, the
device interprets this as a power-off or brown-out
event. The device suspends all I/O operation, shuts off
its connection with the VCC pin, and uses the saved
energy in the capacitor to power the device through the
VCAP pin as it transfers all SRAM data to EEPROM
(see Vcc Power-Off Event). On the next power-up of
VCC, the data is transfered back to SRAM, the capaci-
tor is recharged, and the SRAM operation continues.
Normal Device Operation
CS
SO
SI
SCK
HOLD
VCC Monitor
Normal
SRAM
Operation
VCC (pin 8) System VCC
VCAP (pin 3)
CVCAP Charged to VCC
VSS (pin 4)
System VSS
VCC Power-Off Event
CS
SO
SI
SCK
HOLD
Automatic
Backup
EEPROM
SRAM
V (pin 8)
CC
System VCC
VCAP (pin 3)
CVCAP
Temporary VCC
SRAM to
EEPROM
Transfer
VSS (pin 4)
System VSS
2019 Microchip Technology Inc.
Preliminary
DS20006237B-page 2
