CEC1702
Overview
- Internal Memory - 64k Boot ROM - Two blocks of SRAM, totaling 480KB - Each block can be used for either program or data - 128 Bytes Battery Powered SRAM
- Battery Backed Resources - Power-Fail Status Register - 32 KHz Clock Generator - Week Alarm Timer Interface - Real Time Clock - VBAT-Powered Control Interface - Two Wake-up Input Signals - Optional Latching of Wake-up Inputs - VBAT-Backed 128 Byte Memory
- Four I2C Host Controllers - Allows Master or Dual Slave Operation - Fully Operational on Standby Power - DMA-driven I2C Network Layer Hardware - I2C Datalink Compatibility Mode - Multi-Master Capable - Supports Clock Stretching - Programmable Bus Speed up to 1MHz - Hardware
