CEC1702 Datasheet | Microchip Technology

Feature Included - NVIC Nested Vectored Interrupt Controller - Up to 240 Individually-Vectored Interrupt Sources Supported - 8 Levels of Priority, Individually Assignable By Vector - Chip-Level Interrupt Aggregator supported, to expand number of interrupt sources or reduce number of vectors - System Tick Timer - plete ARM-Standard Debug Support - JTAG-Based DAP Port, prised of SWJ-DP and AHB-AP Debugger Access Functions - Full DWT Hardware Functionality: 4 Data Watchpoints and Execution Monitoring - Full FPB Hardware Breakpoint Functionality: 6 Execution Breakpoints and 2 Literal (Data) Breakpoints - prehensive ARM-Standard Trace Support - Full DWT Hardware Trace Functionality for Watchpoint and Performance Monitoring - Full ITM Hardware Trace Functionality for Instrumented Firmware Support and Profiling - Full TPIU Functionality for Trace Output munication - MPU Feature - 1µS Delay Register - Internal Memory - 64k Boot ROM - Two blocks of SRAM, totaling 480KB - Each block can be used for either program or data - 128 Bytes Battery Powered SRAM - Battery Backed Resources - Power-Fail Status Register - 32 KHz Clock Generator - Week Alarm Timer Interface - Real Time Clock - VBAT-Powered Control Interface - Two Wake-up Input Signals - Optional Latching of Wake-up Inputs - VBAT-Backed 128 Byte Memory - Four I2C Host Controllers - Allows Master or Dual Slave Operation - Fully Operational on Standby Power - DMA-driven I2C Network Layer Hardware - I2C Datalink patibility Mode - Multi-Master Capable - Supports Clock Stretching - Programmable Bus Speed up to 1MHz - Hardware Bus Access “Fairness”...